MCZ33781EK Freescale Semiconductor, MCZ33781EK Datasheet - Page 18

• Manufacturer Part Number: MCZ33781EK
• Description: IC MASTER DSI 2.02 DIFF 32-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33781EK

• Applications: Automotive Systems
• Interface: SPI
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 32-SOIC (7.5mm Width) Exposed Pad, 32-eSOIC, 32-HSOIC
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VSUPn VOLTAGE MONITOR
voltage on the pin drops below the defined voltage threshold
for longer than the voltage threshold mask time, the 33781
will continue to send queued DBUS commands, but not set
any RNE bits in the DnSTAT registers to 1, until either the
DBUS DRIVER /RECEIVER (PHYSICAL LAYER)
blocks on the 33781. These blocks translate the transmit data
to the voltage and current needed to drive the DBUS. They
also detect the response current from the slave devices and
translate that current into digital levels. These circuits can
drive their outputs to the levels listed in
Figure
and Signal modes to minimize common mode noise. The
drivers are disabled in HiZ.
current to recharge the Slave device storage capacitors. In
both Idle and Signal modes it is required to drive the DBUS
load capacitances and control the slew rate over a wide
supply voltage range and load conditions. Current limit, over-
current shutdown and thermal shutdown are included to
protect the device from fault conditions. More information can
be found in the Protection and Diagnostic Features and SPI0
Register and Bit Descriptions sections.
connected between each output and ground. These are the
DBUS common mode capacitors. In addition, a bypass
capacitor is required at V
located close to the IC Pins and provide a low-impedance
path to ground.
18
33781
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
This function monitors the voltage on the V
There are four independent differential bus driver/receiver
The DBUS driver/receiver block diagram is shown in
During Idle mode the driver is required to supply a high
To ensure stability of the bus drivers, capacitors must be
11. The circuit uses a common driver for both the Idle
Over-temp n
Receiver Sum n
Signal Mode Over Current n
Idle Mode Over Current n
Over Temp n
Receiver High n
Signal Mode Over-current n
DSISn
DSIFn
DSISn
DSIFn
hiZn
Receiver Low n
hiZn
Idle Mode Over-current n
SUPn
Over-current
Over-current
Receiver Sum n
Receiver High n
Receiver Low n
. These capacitors must be
Over-temp n
Table
Figure 11. Driver/Receiver Block Diagram
SUPn
5.
Overvoltage
Over-voltage
pin. If the
Generation
Over-current
Over Current
Differential
Generation
Differential
Over Temp
Over-temp
Signal
Adder
Adder
Signal
Sense
Sense
device is reset by the RST pin or the EN bits in the DnEN
registers are first set to zero, and then to one (disabled and
then enabled). By monitoring the RNE bits the MCU will know
that communications have been disrupted and can take the
appropriate action.
state change, and internal signal DSIS controls the signal
level, high or low. DSIR is the slave device response signal to
the logic. This is shown in
another bus. In addition, each bus channel has independent
thermal shutdown protection. Once the channel thermal limit
is reached the bus drivers become high-impedance, the TS
bit is set to a 1 and the EN bit set to 0 in the channel DEN
register. In addition the channel address buffer registers and
pointers are reset. There is a 4 usec filter on Tlim to prevent
false triggering.
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
Table 6. Internal Signal Truth Table
The internal signal DSIF controls the Idle to Signalling
Bus wire faults on a bus do not disrupt communications on
The Differential Signal Generation block converts the
DSIF
X
0
0
1
1
Driver
Driver
DSIS
X
0
1
0
1
Common
Mode
Correction
Correction
Common
Mode
Analog Integrated Circuit Device Data
T
0
0
0
0
1
S
Table
Return Data
Return Data
6.
DSIR
Freescale Semiconductor
0
0
0
High-impedance
High-impedance
DnH
DnL
Signal High
DnH
DnL
Signal Low
DnD
Idle