MAX11041ETC+T Maxim Integrated Products, MAX11041ETC+T Datasheet - Page 9

IC REMOTE CTRLR WIRED 12-TQFN

MAX11041ETC+T

Manufacturer Part Number
MAX11041ETC+T
Description
IC REMOTE CTRLR WIRED 12-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX11041ETC+T

Applications
PDA's, Portable Audio/Video, Smartphones
Interface
I²C
Voltage - Supply
1.6 V ~ 3.6 V
Package / Case
12-TQFN Exposed Pad
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
When a valid keypress occurs, INT goes low, signaling
to the processor that a key has been pressed (see
Figure 3). If the processor reads the FIFO while the key
is still pressed, the key type and current duration of the
keypress is sent. The current keypress information in
the FIFO is not cleared after a read operation if the key
is still pressed. In addition, after a read operation, if the
key is still pressed, INT goes high again until the device
detects another keypress/release, freeing the proces-
sor from polling. Conversely, if the processor chooses
to poll the duration of the keypress, INT stays high at
this time no matter how many times the processor
reads the FIFO. When INT goes low again (from anoth-
er keypress/release), key type and final time duration of
the keypress is available in the FIFO. When the FIFO is
read after the key release, the information from that
keypress is cleared and INT goes high again.
When a valid keypress occurs, INT goes low, signaling
to the processor that a key has been pressed (see
Figure 4). If the processor reads the FIFO after the key
has already been released (or an additional key was
pressed), the key type and final duration time of that
keypress is sent. In addition, the information from the
keypress is cleared and INT goes high again.
The MAX11041 contains an I
data communication with a host processor (SCL and
SDA). The interface supports a clock frequency up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply. Figure 5 details the
read and write formats.
Figure 5. Read/Write Formats
WRITE FORMAT
READ FORMAT
Reading the FIFO While the Key is Still Pressed
START
START
S
S
Reading the FIFO After the Key has Released
5 BITS
5 BITS
ADDRESS
ADDRESS
BYTE 0
BYTE 0
A1 A0
A1 A0
____________________________________________________________________________________
R/W
R/W
0
1
Digital Serial Interface
2
C-compatible interface for
ACK
ACK
A
A
REG DATA
CONTROL
C7–C0
BYTE 1
CHIP ID
BYTE 1
I7–I0
ACK
ACK
A
A
STOP
P
REG DATA
CONTROL
BYTE 2
C7–C0
Wired Remote Controller
The only write to the MAX11041 that is possible is to the
control register (C7–C0). Use the following sequence to
write to the control register (see Figure 5):
1) After generating a START condition (S), address the
2) Send the appropriate data bytes to program the
3) Generate a STOP condition (P).
To read the control register and key type/duration stored
in FIFO, use the following sequence (see Figure 5):
1) After generating a START condition (S), address the
2) The MAX11041 sends the 8-bit chip ID I7–I0.
3) The MAX11041 sends the contents of the control
MAX11041 by sending the appropriate slave
address byte with its corresponding R/W bit set to a
0 (see the Slave Address and R/W Bit section). The
MAX11041 answers with an ACK bit (see the
Acknowledge Bits section).
control register (C7–C0). The MAX11041 answers
with an ACK bit.
MAX11041 by sending the appropriate slave
address byte with its corresponding R/W bit set to a
1 (see the Slave Address and R/W Bit section). The
MAX11041 answers with an ACK bit (see the
Acknowledge Bits section).
Afterwards, the master must send an ACK bit.
register (C7–C0) starting with the most significant
bit. Afterwards, the master must send an ACK bit.
ACK
A
KEY TYPE
BYTE 3
K7–K0
SLAVE TO MASTER
MASTER TO SLAVE
ACK
A
DURATION
OF, T6–T0
BYTE 4
KEY
Write Format
ACK
Read Format
A
STOP
P
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