NCN6804MNR2G ON Semiconductor, NCN6804MNR2G Datasheet
NCN6804MNR2G
Specifications of NCN6804MNR2G
NCN6804MNR2GOSTR
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NCN6804MNR2G Summary of contents
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... DDPA CRD_DETA CRD_C4A CRD_C8A CRD_I/OA CRD_RSTA CRD_CLKA CRD_VCCA ORDERING INFORMATION Device NCN6804MNR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1 http://onsemi.com MARKING DIAGRAM 1 NCN 1 32 ...
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VBAT 10mF L1A VDD 0.1mF VDD INT CS CLK_SPI MISO MOSI CLK_IN I/O EN_RPU VDD GNDD Figure 1. Typical Interface Application http://onsemi.com L2A L1B L2B GND SMART CARD A S1 DET CRD_DETA GND 10mF 1 ...
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VDD 50 k INTERRUPT BLOCK INT 24 32 VDD VDD MISO 30 MOSI CLK_SPI 28 VDD LOGIC CONTROL CLOCK 26 CLK_IN I/O MUX I EN_RPU 31 Exposed Pad GNDD 33 GND INT#A DET#A DET#B ...
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PIN FUNCTION AND DESCRIPTION PIN Name Type Address pin (Chip Identification pin) – allows having in parallel NCN6804 devices (4 inter- faces) managed by 1 Chip Select pin only (CS) – multiple interface application ...
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PIN FUNCTION AND DESCRIPTION PIN Name Type 25 I/O I/O This pin is connected to an external micro−controller (mC) interface. A bi−directional level translator adapts the serial I/O signal between the smart card and the mC. The level translator is ...
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MAXIMUM RATINGS (Note 3) Rating DC/DC Converter Power Supply Voltage (V Power Supply from Microcontroller Side (V External Card Power Supply (Card A and B) Digital Input Pins Digital Output Pins (I/O, MISO, INT) Smart Card Output Pins Smart Card ...
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POWER SUPPLY SECTION (−40°C to +85°C, unless otherwise noted) Pin Symbol 12 Power Supply (V sup 12 Operating current – All Card Pins Unloaded, CLK_IN=Low sup V sup V sup 12 Standby Supply ...
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DIGITAL INPUT/OUTPUT SECTION CLK_IN, I/O, CLK_SPI, MOSI, MISO, CS, INT, EN_RPU Pin Symbol 26 F Input Asynchronous Clock Duty Cycle = 50% CLK_IN @ Input Clock Rise ...
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SMART CARD INTERFACE SECTION Note: Digital inputs undershoot v 0.30V to ground, digital inputs overshoot < V Pin Symbol 6,19 CRD_RSTA/B @ CRD_VCCA/B = 1.8 V, 3 Output RESET Output RESET V OL ...
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PROGRAMMING Write Register " WRT_REG (Is Low Only) Similar to the NCN6001, the NCN6804’s WRT_REG register handles 3 command bits [b5:b7] and 5 data bits [b0:b4] as depicted in Tables 1 and 2. These bits are concatenated into 1 byte ...
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Table 1. WRT_REG BIT DEFINITIONS 000 or ( 010 then b3 Case 00 CRD_CLKA = Low Case 01 CRD_CLKA = CLK_IN Case 10 CRD_CLKA = ...
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Table 2. WRT_REG BIT DEFINITIONS AND FUNCTIONS ADRESS MSB0 A/B CRD_RST 0 S1 A/B CRD_RST 0 S1 A/B CRD_RST 0 S1 A/B CRD_RST 1 1 A/B CRD_RST CRD_CLK ...
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Asynchronous Mode In this mode, the S1 pin is used to define the physical address (by comparison with the bit b6 (MOSI)) of the interfaces when a bank NCN6804 (total of 4 interfaces) shares the same ...
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CS CRD_VCC CRD_IO CRD_CLK CRD_C4 CRD_C8 CRD_RST Figure 3. Startup CRD_VCC Sequence Figure 4. Measured Typical Startup CRD_VCC Sequence At powerup, the CRD_VCCA/B turn−on time depends upon the current capability of the DC/DC converter associated with the external inductor L ...
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Figure 6. Figure 7: Start Up Sequence with ATR. Powerdown Sequence The NCN6804 provides an automatic Power Down sequence, according to the ISO7816−3 specifications. When a power down sequence is enabled the communication session terminates immediately. The sequence is launched ...
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EN_RPU R1 I/O 1 SYNC MOSI/b2 Q5 From MOSI decoding GND MOSI/b3 The transaction is valid when the Chip Select pin is Low, the I/O signal being Open Drain or Totem Pole on either sides. ...
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Table 7. INTERRUPT RESET LOGIC TABLE Interrupt Source Interrupt Clearance (INT reset to HIGH) CRD_VCCA/B / {b1, b0} pro- (INT set to LOW) CS Card Insertion L Card Extraction L Over Load L In order to know the source of ...
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SPI Port The product communicates to the external micro controller by means of a serial link using a Synchronous Port Interface protocol, the CLK_SPI being Low or High during the idle state. The NCN6804 is not intended to operate as ...
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CS MPU Enables B7 B6 Clock SPI_CLK CHIP ADDRESS MSB MOSI SET_RST SET_CLK SET_VCC ADDRESS DECODE MISO Line = High Impedance MISO Special Mode MISO Line = High Impedance MISO Normal Mode Since the 2 dual circuits present in the ...
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DC/DC Operation The power conversion is based on a full bridge structure able to handle either step up or step down power supply (see GND CMD_1.8V G_Q1 CMD_3.0V CMD_5.0V G_Q3 CMD_STOP G_HIZ G_Q4 G_Q2 G_Q7 In order ...
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Charge CRD_VCC off Q1/Q4 Q2/Q3 Q5/Q6 IL CRD_VCC Voltage Regulated CRD_VCC Figure 17. Theoretical DC/DC Operating Waveforms When the CRD_VCC is programmed to zero volt, or when the card is extracted from the socket, the active pull ...
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100 ICRD_VCC (mA) Figure 20. Output Current Limit: Output voltage CRD_VCC (1.8 V, 3 the other hand, the circuit is designed to make ...
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CLOCK_IN CLOCK : 1 CLOCK : 2 CLOCK : CRD_CLK CLOCK programming is activated by the logic state Figure 22. Typical Clock Divider Synchronization VCC CLK_IN B2 Programming B3 CRD_CLK Division SYNC B0 B1 ...
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Input Schmitt Triggers All the Logic Input pins have built in Schmitt trigger circuits to protect the NCN6804 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted Figure 24. OUTPUT V BAT ON OFF 0.3 VBAT ...
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... *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...