MR0D08BMA45 EverSpin Technologies Inc, MR0D08BMA45 Datasheet

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... I/O Voltage range supports wide +1.65 to +3.6 Volt interfaces • Fast 45 ns read/write cycle • SRAM compatible timing • Unlimited read & write endurance • Data always non-volatile for >20-years at temperature • RoHS-compliant small footprint BGA package BENEFITS • One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems for simpler, more efficient designs • Improves reliability by replacing battery-backed SRAM INTRODUCTION The MR0D08B is a dual power supply 1,048,576-bit magnetoresistive random access memory (MRAM) de- vice organized as 131,072 words of 8 bits. It supports I/O voltages from +1.65 to +3.6 volts. The MR0D08B offers SRAM compatible 45ns read/write timing with unlimited endurance. Data is always non-volatile for greater than 20-years ...

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... Not Connect NC No Connection, Ball D3, H1, H6, G2 Reserved for Future Expansion Everspin Technologies © 2009 Figure 1.1 Block Diagram OUTPUT ENABLE ROW COLUMN DECODER DECODER 8 SENSE AMPS 128Kx 8 BIT MEMORY ARRAY FINAL 8 WRITE DRIVERS WRITE ENABLE Table 1.1 Pin Functions 2 Document Number: MR0D08B Rev. 1, 10/2009 MR0D08B 8 8 OUTPUT BUFFER 8 WRITE ...

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DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View high low don’t care 1 Hi-Z = high impedance 2 Everspin Technologies © 2009 ...

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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Parameter Core Supply voltage 2 I/O Power Supply voltage Voltage on any pin 2 Output current per pin Package power dissipation Temperature under bias Storage Temperature Lead temperature during solder (3 minute max) Maximum magnetic field during write Maximum magnetic field during read or standby Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera- 1 tion should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. All voltages are referenced Power dissipation capability depends on package characteristics and use environment. 3 Everspin Technologies © 2009 Table 2.1 Absolute Maximum Ratings ...

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Electrical Specifications Parameter Core Power supply voltage I/O Power supply voltage Write inhibit voltage Write inhibit voltage Input high voltage (V =1.65-2.2V) DDQ Input high voltage (V =2.2-2.7V) DDQ Input high voltage (V =2.7-3.6V) DDQ Input low voltage (V =1.65-2.2V) DDQ Input low voltage (V =2.2-2.7V) DDQ Input low voltage (V =2.7-3.6V) DDQ Temperature under bias ≤ Write inhibit occurs when either V i DDQ DD (min). See Power Up and Power Down Sequencing. ...

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... Electrical Specifications Power Up and Power Down Sequencing MRAM is protected from write operations whenever exceeds V (min) and erations can start. This time allows memory power supplies to stabilize. The E and W control signals should track V high for the startup time. In most systems, this means that these signals should be pulled up with a resis- tor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where either V tected and a startup time must be observed when power returns above V STARTUP TIME V WI WRITES INHIBITED ...

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Electrical Specifications Parameter Input leakage current Output leakage current Output low voltage (V =1.65-2.2V@ 0.1mA) DDQ Output low voltage (V =2.2-2.7V@ 0.1mA) DDQ Output low voltage (V =2.7-3.6V@ 2.1 mA) DDQ Output high voltage (V =1.65-2.2V@ - 0.1 mA) DDQ Output high voltage (V =2.2-2.7V@ -0.1 mA) DDQ Output high voltage (V =2.7-3.6V@ -1.0 mA) DDQ Parameter AC active supply current - read modes ( mA max) OUT DD AC active supply current - write modes (V = max standby current (V = max ...

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TIMING SPECIFICATIONS Parameter Address input capacitance Control input capacitance Input/Output capacitance f = 1.0 MHz °C, periodically sampled rather than 100% tested. 1 DDQ DDQ(typ A Parameter Logic input timing measurement reference level Logic output timing measurement reference level Logic input pulse levels Output load voltage (V ) for low & high impedance L parameters (Figure 3.1) Output load resistor (R1) for all other timing Output load resistor (R2) for all other timing Output Everspin Technologies © 2009 Table 3.1 Capacitance Symbol Table 3.2 AC Measurement Conditions ...

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Timing Specifications Read Mode Parameter Read cycle time Address access time Enable access time 2 Output enable access time Output hold from address change Enable low to output active 3 Output enable low to output active Enable high to output Hi-Z 3 Output enable high to output Hi high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be 1 minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage (ADDRESS) Q (DATA OUT) NOTE: Device is continuously selected (E ≤ (ADDRESS) E (CHIP ENABLE) G (OUTPUT ENABLE) Q (DATA ...

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Timing Specifications Parameter Write cycle time 2 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Write pulse width (G high) Write pulse width (G low) Data valid to end of write Data hold time Write low to data Hi-Z 3 Write high to output active 3 Write recovery time All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. 2 This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given 3 voltage or temperature, t (max) < t WLQZ A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA ...

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Timing Specifications Parameter Write cycle time 2 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Enable to end of write (G high) Enable to end of write (G low) 3 Data valid to end of write Data hold time Write recovery time All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address goes low at the same time or after W goes low, the output will remain in a high-impedance state goes high at the 3 same time or before W goes high, the output will remain in a high-impedance state. A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) Everspin Technologies ...

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Timing Specifications Table 3.6 Write Cycle Timing 3 (Shortened t Parameter Write cycle time 2 Address set-up time Address valid to end of write (G high) Address valid to end of write (G low) Write pulse width Data valid to end of write Data hold time Enable recovery time Write recovery time 3 Write to enable recovery time 3 All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus 1 contention conditions must be minimized or eliminated during read and write cycles goes low at the same time or after W goes low, the output will remain in a high impedance state. After has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address goes low at the same time or after W goes low, the output will remain in a high-impedance state goes high at the 3 same time or before W goes high, the output will remain in a high-impedance state. Table 3.6 Write Cycle Timing ...

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... ORDERING INFORMATION Part Number MR0D08BMA45 MR0D08BMA45R Everspin Technologies © 2009 Figure 4.1 Part Numbering System Table 4.1 Available Parts Description Dual Supply 128x8 MRAM 48-BGA Dual Supply 128x8 MRAM 48-BGA Tape & Reel 13 MR0D08B Carrier (Blank= Tray,R=Tape & Reel) Speed ( ns) Package (MA = FBGA) Temperature Range (Blank +70 °C) Revision (B = Revision) Data Width (08 = 8-Bit) Type ...

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Mechanical Drawings BOTTOM VIEW 1. Dimensions in Millimeters. 2. Dimensions and tolerances per ASME Y14.5M - 1994. 3. Maximum solder ball diameter measured parallel to DATUM A 4. DATUM A, the seating plane is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. Everspin Technologies © 2009 Figure 5.1 FBGA TOP VIEW Print Version Not To Scale 14 MR0D08B SIDE VIEW Document Number: MR0D08B Rev. 1, 10/2009 ...

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REVISION HISTORY Revision Date 0 Aug 24, 2009 Initial Product Concept 1 Oct 22, 2009 Unless Otherwise Noted, This is a Production Product - This product conforms to specifications per the terms of the Everspin standard warranty. The product has completed Everspin internal qualification testing and has reached production status. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Asia/Pacific Everspin Technologies 1300 N. Alma School Road, CH-409 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Wokingham, United Kingdom +44 (0)118 907 6155 Japan ...