NCP3170ADR2G ON Semiconductor, NCP3170ADR2G Datasheet - Page 2

• Manufacturer Part Number: NCP3170ADR2G
• Description: IC BUCK SYNC/ASYNC ADJ 3A 8SOIC
• Manufacturer: ON Semiconductor
• Series: -r
• Type: Step-Down (Buck), PWM - Current Moder

Specifications of NCP3170ADR2G

• Internal Switch(s): Yes
• Synchronous Rectifier: Both
• Number Of Outputs: 1
• Voltage - Output: 0.8 V ~ 12.8 V
• Current - Output: 3A
• Frequency - Switching: 500kHz
• Voltage - Input: 4.5 V ~ 18 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

COMP
PIN FUNCTION DESCRIPTION
EN
PG
FB
Pin
1
2
3
4
5
6
7
8
Reference
Pin Name
COMP
PGND
AGND
Circuit
ORing
VSW
VIN
PG
FB
EN
+
−
Soft Start
998 mV
867 mV
728 mV
The power ground pin is the high current path for the device. The pin should be soldered to a large copper
area to reduce thermal resistance. PGND needs to be electrically connected to AGND.
The input voltage pin powers the internal control circuitry and is monitored by multiple voltage comparators.
The VIN pin is also connected to the internal power PMOS switch and linear regulator output. The VIN pin
has high di/dt edges and must be decoupled to ground close to the pin of the device.
The analog ground pin serves as small−signal ground. All small−signal ground paths should connect to the
AGND pin and should also be electrically connected to power ground at a single point, avoiding any high
current ground returns.
Inverting input to the OTA error amplifier. The FB pin in conjunction with the external compensation serves to
stabilize and achieve the desired output voltage with current mode compensation.
The loop compensation pin is used to compensate the transconductance amplifier which stabilizes the opera-
tion of the converter stage. Place compensation components as close to the converter as possible. Connect
a RC network between COMP and AGND to compensate the control loop.
Enable pin. Pull EN to logic high to enable the device. Pull EN to logic low to disable the device. Do not leave
it open.
Power good is an open drain 500 mA pull down indicating output voltage is within the power good window. If
the power good function is not used, it can be connected to the VSW node to reduce thermal resistance. Do
not connect PG to the VSW node if the application is turning on into pre−bias.
The VSW pin is the connection of the drains of the internal N and P MOSFETS. At switch off, the inductor will
drive this pin below ground as the body diode and the NMOS conducts with a high dv/dt.
UVLO
POR
+
+
+
−
−
−
+
−
AGND
Σ
Soft Start
Complete
Compensation
Oscillator
Slope
Figure 2. NCP3170 Block Diagram
Control
Power
(PC)
Temperature
Protection
Over
S
R
http://onsemi.com
CLR
SET
VDD
Q
Q
2
Detection
logic
Pulse by
Current
Current
Pulse
Limit
Zero
Description
HS
LS
hs
Voltage
Clamp
Driver
VSW
VCW
VCL
PDRV
NDRV
VCW
VCL
VIN
PGND
VIN
0.030V/A
Current
Sense
VSW