DS33W41+ Maxim Integrated Products, DS33W41+ Datasheet - Page 34

• Manufacturer Part Number: DS33W41+
• Description: IC MAPPING ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33W41+

• Applications: Data Transport
• Interface: Parallel/Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
8.
Functional Description
The DS33X162 family of devices provide interconnection and mapping functionality between Ethernet Systems and
WAN Time-Division Multiplexed (TDM) systems such as T1/E1/J1, HDSL, T3/E3, and SONET/SDH. The device is
composed of up to two 10/100/1000 Ethernet MACs, up to 16 Serial Ports, a Arbiter, GFP/HDLC/cHDLC/X.86
(LAPS) Mappers, a DDR SDRAM interface, and control ports.
Ethernet traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) to be transmitted over the WAN Serial
Interfaces. The WAN Serial Interfaces also receive encapsulated Ethernet frames and transmit the extracted
frames over the Ethernet ports.
The LAN interface consists of Ethernet MACs using one of two physical layer protocols. The interface can be
configured with up to two 10/100Mbps MII/RMII ports or a single GbE GMII port. The MII/RMII and GMII interfaces
allow connection to commercially available Ethernet PHY and MAC devices.
The WAN physical interface supports 8 serial data streams up to 52Mbps each. The DS33X162 and DS33X161
support an additional 8 serial data streams with data rates up to 2.5Mbps each. The WAN serial interfaces receive
encapsulated Ethernet frames and transmit the extracted frames over the Ethernet ports. The WAN serial ports can
operate with a gapped clock, and can be connected to a framer, electrical LIU, optical transceiver, or T/E-Carrier
transceiver for transmission to the WAN. The Serial Interfaces can be seamlessly connected to the Maxim
T1/E1/J1 Framers, Line Interface Units (LIUs), and Single-Chip Transceivers (SCTs). The WAN interfaces can also
be seamlessly connected to the Maxim T3/E3/STS-1 Framers, LIUs, and SCTs to provide T3, E3, and STS1
connectivity.
Ethernet frames are queued and stored in an external 32-bit DDR SDRAM. The DDR SDRAM controller enables
connection to a 256Mb SDRAM without external glue logic, at clock frequencies up to 125MHz. The SDRAM is
used for the LAN Data, WAN Data, Frame Extraction, and Frame Insertion Queues. The user can program a “near
full threshold” (watermark) for the LAN and WAN queues that can be used to initiate automatic flow control. The
43
+1 payload and Barker sequence scrambling.
device also provides the capability for X
Microprocessor control can be accomplished through a 8-bit Micro controller port or SPI Bus. The device has a
125MHz DDR SDRAM controller and interfaces to a 32-bit wide 256Mb DDR SDRAM via a 16-bit data bus. The
DDR SDRAM is used to buffer data from the Ethernet and WAN ports for transport.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.
Rev: 063008
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