DS33M33N+ Maxim Integrated Products, DS33M33N+ Datasheet - Page 7

• Manufacturer Part Number: DS33M33N+
• Description: IC MAPPER ETHERNET 256CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33M33N+

• Applications: Data Transport
• Interface: SPI
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 256-CSBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.3
1.3.1 STS-3/STM-1 SerDes
1.3.2 STS-3/STM-1 Framer and Formatter
1.3.2.1 STS-3/STM-1 Formatter with Transport Overhead Insertion
1.3.2.2 STS-3/STM-1 Framer with Transport Overhead Extraction
Rev: 111908
___________________________________________________ DS33M30/M31/M33 ABRIDGED DATA SHEET
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SONET/SDH
SerDes with clock recovery at 155.52Mbps interface for STS-3/STM-1 data stream
LVDS/LVPECL levels for glueless interconnect to 155.52Mbps optical transceiver device
User-configurable scrambling for transmit STS-3/STM-1 bit stream
User-configurable TOH bytes insertion for framing (A1, A2), Section trace (J0), Section BIP-8 (B1), Section
orderwire (E1), Section user channel (F1), Section Data Communication Channel (DCC) (D1-D3), STS-1
pointers (H1, H2, H3), Line BIP-8 (B2), automatic protection switching (APS) channel (K1, K2), Line DCC
(D4-D12), synchronization status message (S1), line Remote Error Indication (REI) (M1), and line
orderwire (E2). Note: B1 and B2 are configured as error masks
Automatic calculation and insertion of Section BIP-8 (B1) and Line BIP-8 (B2)
User configurable insertion of AIS-P, and AIS-L
Programmable generation of H1, H2, and H3 bytes as an error mask
All TOH bytes can be inserted from the associated transmit STS-3 transport overhead input port or
software accessible internal registers
Automatic or manual generation of line remote error indication (REI-L) and line remote defect indication
(RDI-L)
Programmable insertion of framing errors, B1 errors, B2 errors, and invalid pointer
Insertion of HDLC data stream into section DCC (D1-D3), line DCC (D4-D12), TOH DCC (D1-D12), or
section user channel (F1)
Insertion of trace ID message into section trace (J0)
Frame synchronization for STS-3 compliant to GR-253 so that SEF defect is not detected more than an
average of once every six minutes in the presence of STS-1 BER of 10-3
Optional descrambler of incoming STS-1 data stream with polynomial of 1+x6+x7
Extraction of all TOH bytes (per LTE requirement): Framing (A1, A2), Section trace (J0), Section BIP-8
(B1), Section orderwire (E1), Section user channel (F1), Section Data Communication Channel (DCC) (D1-
D3), STS-1 pointers (H1, H2, H3), Line BIP-8 (B2), automatic protection switching (APS) channel (K1, K2),
Line DCC (D4-D12), synchronization status message (S1), Line Remote Error Indication (REI) (M1), and
Line orderwire (E2)
All TOH bytes are presented on the associated receive STS-3 transport overhead output port and software
accessible internal registers
Detection of STE and LTE defects including LOS, LOF, SEF, COFA, and AIS-L
Fully programmable automatic downstream path AIS (AIS-P) insertion upon detection of LOS, LOF, TIM-S,
and/or AIS-L
Detection of STE and LTE defects including RDI-L, APS unstable, and sync message change (S1)
Detection and accumulation of framing errors (A1/A2), OOF occurrences, section BIP-8 (B1) errors (bit or
block basis), line BIP-8 (B2) errors (bit or block basis), and line remote error indications (REI-L)
Extraction of HDLC data stream from Section DCC (D1-D3), Line DCC (D4-D12), TOH DCC (D1-D12), or
Section user channel (F1)
Extraction of trace ID message from Section trace (J0)
Two line BIP-8 parity (B2) bit error rate (BER) measurement circuits with separate software programmable
detection and clearing settings
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