UJA1069TW24/3V0,51 NXP Semiconductors, UJA1069TW24/3V0,51 Datasheet - Page 11

• Manufacturer Part Number: UJA1069TW24/3V0,51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/3V0,51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 3V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280016518; UJA1069TW24/3V0-T; UJA1069TW24/3V0-T

NXP Semiconductors
UJA1069_3
Product data sheet
6.2.6 Sleep mode
6.2.7 Flash mode
When an interrupt event occurs the application software has to read the Interrupt register
within t
entered. If the application has read out the Interrupt register within the specified time, it
can decide whether to switch into Normal mode via an SPI access or to stay in Standby
mode.
The following operations are possible from Standby mode:
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled
external supplies are switched off entirely, resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out mode or is completely off.
Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any
operation of the microcontroller. The INH/LIMP output is floating in parallel and pin V1 is
disabled. It is also possible for V3 to be ON, OFF or in Cyclic mode to supply external
wake-up switches.
If the watchdog is not disabled in software, it will continue to run and force a system reset
upon overflow of the programmed period time. The SBC enters Start-up mode and pin V1
becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.
Depending on the application, the following operations can be selected from Sleep mode:
Flash mode can only be entered from Normal mode by entering a specific Flash mode
entry sequence. This fail-safe control sequence comprises three consecutive write
accesses to the Mode register, within the legal windows of the watchdog, using the
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Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start
sequences after reset)
Wake-up by activity on the LIN-bus via an interrupt signal to the microcontroller
Wake-up by bus activity on the LIN-bus via a reset signal
Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid
and wake-up from an external application not connected to the SBC)
Wake-up by increasing the microcontroller supply current with a reset signal
Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller
Wake-up due to a falling edge at pin WAKE forcing a reset signal
Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow different
start sequences after reset
Wake-up by activity on the LIN-bus or falling edge at pin WAKE
An overload on V3, only if V3 is in a cyclic or in continuously ON mode
RSTN(INT)
. Otherwise a fail-safe system reset is forced and Start-up mode will be
Rev. 03 — 10 September 2007
LIN fail-safe system basis chip
UJA1069
© NXP B.V. 2007. All rights reserved.
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