Z16M1720ASC Zilog, Z16M1720ASC Datasheet - Page 88

• Manufacturer Part Number: Z16M1720ASC
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z16M1720ASC

• Applications: Ethernet Controller
• Interface: SPI Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Package / Case: *
• Mounting Type: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

74
EEPROM Register
Address: SELECT 2Fh
Name: Bus Control
Type: Read/Write
PS012002-1201
Bit Placement
Bit 0
Bit 1
Bit 2
Z86017/Z16017 PCMCIA Interface Solution
Product Specification
Table 58.
Bit Name
EN_BHE_POL
EN_16_DUECE
EN_DIV_ADDR
Bus Control Register: Address 2Fh
Description
When this bit is cleared, it enables the polarity of the
ATA_BHE output to be active High. When it is set, it
enables the polarity to be active Low. At Power-On Reset,
this bit defaults to clear. Also see Register 00h (Table 11).
When this bit is set, it enables word-to-byte access when in
memory mode. This mode allows a 16-bit host to access 8-
bit peripherals. When cleared, this bit disables word-to-
byte access mode. When set, this bit enables the ZX6017 to
generate two peripheral write or read strobes on the local
peripheral side when the host writes or reads 16 bits of
data. This mode allows a 16-bit host to read/write to 8-bit
peripheral device registers with one 16-bit access. When
this mode is enabled, and the ZX6017 is in memory mode,
the host gains access to the peripheral’s 8-bit registers by
selecting an even address usingPC_HCE1. The ZX6017
asserts the PC_WAIT pin, which allows the write or read
strobe to the peripheral device to be controlled through the
“DUECE_WIDTH” and “DUECE_ACCESS_DLY” bits in
the Bus control Register 2Fh and the externals peripherals
IOCHRDY signal if present (Figure 10). Figure 11 depicts
the PCMCIA to local peripheral data path information.
When set, this bit indicates that PCMCIA host address
lines A3, A2 and A1 are mapped to the local interface
address lines A2, A1 and A0. When cleared, PCMCIA
address lines A2, A1 and A0 are mapped to local interface
A2, A1 and A0.
Programming Internal Registers