MC33394DWB Freescale Semiconductor, MC33394DWB Datasheet - Page 21

• Manufacturer Part Number: MC33394DWB
• Description: IC POWER SUPPLY MULT-OUT 54-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33394DWB

• Applications: Motorola MPC55x, MPC56x Microprocessors
• Interface: SPI Serial
• Voltage - Supply: 4 V ~ 26.5 V
• Package / Case: 54-SOIC (0.300", 7.50mm Width) Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

4.15. SPI Interface to Microcontroller (Serial
Peripheral Interface)
(Data Output), CS (Chip Select) and SCLK. Refer to Figure 3
for the 33394 SPI timing information. The delay, which is
needed from CS leading edge active to the first SCLK leading
edge transition (0 to 1) is approximately 125 ns. The SCLK
rate is a maximum of 5.0 MHz. The SPI function will provide
control of such 33394 features as VREFn regulator turn on/off,
VREFn fault reporting and CAN wake up feature activation.
Refer to Figure 7 & Figure 8 for the data and status bit
assignments for the 16 bit SPI data word exchange.
4.15.1. CS (Chip Select) Pin
with through the use of the CS pin. Whenever the pin is in a
logic high state, data can be transferred from the MCU to the
33394 and vice versa. Clocked—in data from the MCU is
transferred to the 33394 shift register and latched in on the
falling edge of the CS signal. On the rising edge of the CS
signal, output status information is transferred from the output
status register into the device’s shift register. Whenever the
CS pin goes to a logic high state, the DO pin output is enabled
allowing information to be transferred from the 33394 to the
MCU. To avoid any spurious data, it is essential that the
transition of the CS signal occur only when SCLK is in a logic
low state.
4.15.2. SCLK (System Clock) Pin
of the 33394. The serial input (DI) data is latched into the input
shift register on the rising edge of the SCLK. The serial output
pin (DO) shifts data information out of the shift register also on
the rising edge of the SCLK signal. It is essential that the SCLK
33394 SPI Registers:
Serial Input Data/Control
Bit Definitions:
Bit 15 to 8 = 0
Bit Definitions:
Bit 7 — WKUP: WAKEUP activation. WKUP = 1: WAKEUP pin will signal CAN bus activity
Bit 6 — CAN_EN: Enables CAN receiver, will draw small current during power off
Bit 5 — VPP_V: Set VPP reference to 5V (1) or 3.3V (0), default is 5V
Bit 4 — EN_VPP: – Used to turn the VPP regulator off and on from the MCU
Bit 3 — VSEN: – Used to turn the VSEN regulator off and on from the MCU
Bit 2 — VREF3: – Used to turn the VREF3 regulator off and on from the MCU
Bit 1 — VREF2: – Used to turn the VREF2 regulator off and on from the MCU
Bit 0 — VREF1: – Used to turn the VREF1 regulator off and on from the MCU
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Default Value
Bit
Name
Default Value
Bit
Name
The pins specified for this function are: DI (Data Input), DO
The system MCU selects the 33394 to be communicated
The shift clock pin (SCLK) clocks the internal shift registers
WKUP
15
0
1
7
Freescale Semiconductor, Inc.
CAN_EN
For More Information On This Product,
14
0
1
6
Figure 7. SPI Input Data/ Control Register
Go to: www.freescale.com
VPP_V
13
0
1
5
33394
EN_VPP
12
0
1
4
pin be in a logic low state whenever the chip select pin (CS)
makes any transition. For this reason, it is recommended
though not necessary, that the SCLK pin is commanded to a
low logic state as long as the device is not accessed (CS in
logic low state). When CS is in a logic low state, any signal at
the SCLK and DI pin is ignored and the DO is tri—stated (high
impedance).
4.15.3. DI (Data Input) Pin
latched into the input register on the rising edge of SCLK. A
logic high state present on DI will program a specific function
(see Figure 7 for the data bits assignments for the 16 bit SPI
data word exchange.). The change will happen with the falling
edge of the CS signal. To program the specific function of the
33394 a 16 bit serial stream of data is required to be entered
into the DI pin starting with LSB. For each rising edge of the
SCLK while CS is logic high, a data bit instruction is loaded into
the shift register per the data bit DI state. The shift register is
full after 16 bits of information have been entered. To preserve
data integrity, care should be taken to not transition DI as
SCLK transitions from a low to high logic state.
4.15.4. DO (Data Output) Pin
register. The DO pin remains tri—state until the CS pin goes
to a logic high state. See Figure 8 for the status bits
assignments for the 16–bit SPI data word exchange. The CS
positive transition will make LSB status available on DO pin.
Each successive positive SCLK will make the next bit status
available.
first—in—first—out protocol with both input and output words
transferring the Least Significant Bit (LSB) first.
The DI pin is used for serial data input. This information is
The serial output (DO) pin is the output from the shift
VSEN
11
The
0
1
3
DI/DO
VREF3
10
0
1
2
shifting
VREF2
of
0
9
1
1
data
follows
0 (LSB)
VREF1
0
8
1
21
a