DS90CR285SLC National Semiconductor, DS90CR285SLC Datasheet
DS90CR285SLC
Specifications of DS90CR285SLC
Available stocks
Related parts for DS90CR285SLC
DS90CR285SLC Summary of contents
Page 1
... PLL requires no external components n Both devices are offered in a Low profile 56-lead TSSOP package n DS90CR285SLC is offered ball, 0.8mm fine pitch ball grid array (FBGA) package for use with the DS90CR286ASLC n Rising edge data strobe n Compatible with TIA/EIA-644 LVDS standard > ...
Page 2
Pin Diagrams for TSSOP Packages DS90CR285 Typical Application www.national.com DS012910-21 2 DS90CR286 DS012910-22 DS012910-23 ...
Page 3
... Differential Input Low Threshold TL I Input Current IN (Note 1) Maximum Package Power Dissipation DS90CR285MTD DS90CR285SLC DS90CR286MTD Package Derating: −0.3V to +4V DS90CR285MTD −0. 0.3V) CC DS90CR285SLC −0. 0.3V) CC DS90CR286MTD −0. 0.3V) ESD Rating CC −0. 0.3V) (HBM, 1 100 pF) CC Recommended Operating Continuous Conditions +150˚C − ...
Page 4
Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified Symbol Parameter TRANSMITTER SUPPLY CURRENT I Transmitter Supply Current CCTW Worst Case (with Loads) Transmitter Supply Current I CCTZ Power Down RECEIVER SUPPLY CURRENT I Receiver Supply Current ...
Page 5
Transmitter Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol Parameter TPPos3 Transmitter Output Pulse Position for Bit3 TPPos4 Transmitter Output Pulse Position for Bit4 TPPos5 Transmitter Output Pulse Position for Bit5 TPPos6 Transmitter ...
Page 6
Receiver Switching Characteristics Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified Symbol Receiver Input Strobe Position for Bit 0 (Note 6)( Figure 17 ) RSPos0 RSPos1 Receiver Input Strobe Position for Bit 1 RSPos2 Receiver Input ...
Page 7
AC Timing Diagrams (Continued) DS012910-5 FIGURE 3. DS90CR286 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. DS90CR285 (Transmitter) Input Clock Transition Time Note 8: Measurements DIFF Note 9: TCCS measured between earliest and latest LVDS ...
Page 8
AC Timing Diagrams FIGURE 7. DS90CR286 (Receiver) Setup/Hold and High/Low Times FIGURE 8. DS90CR285 (Transmitter) Clock In to Clock Out Delay FIGURE 9. DS90CR286 (Receiver) Clock In to Clock Out Delay FIGURE 10. DS90CR285 (Transmitter) Phase Lock Loop Set Time ...
Page 9
AC Timing Diagrams (Continued) FIGURE 11. DS90CR286 (Receiver) Phase Lock Loop Set Time FIGURE 12. Seven Bits of LVDS in Once Clock Cycle FIGURE 13. 28 ParalIeI TTL Data Inputs Mapped to LVDS Outputs DS012910-14 DS012910-15 9 DS012910-16 www.national.com ...
Page 10
AC Timing Diagrams FIGURE 16. Transmitter LVDS Output Pulse Position Measurement www.national.com (Continued) FIGURE 14. Transmitter Powerdown DeIay FIGURE 15. Receiver Powerdown Delay 10 DS012910-17 DS012910-18 DS012910-19 ...
Page 11
AC Timing Diagrams (Continued) FIGURE 17. Receiver LVDS Input Strobe Position 11 DS012910-28 www.national.com ...
Page 12
AC Timing Diagrams C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM Cable Skew (type, length) + Source Clock ...
Page 13
Pin Descriptions (Continued) DS90CR285 SLC64A (FBGA) Package Pin Summary — Channel Link Transmitter Pin Name I/O No. GND I 5 Ground pins for TTL inputs. PLL Power supply pin for PLL. CC PLL GND I 2 Ground ...
Page 14
Pin Descriptions (Continued) DS90CR285 SLC64A (FBGA) Package Pin Description — Channel Link Transmitter By Pin E3 TxIN7 E4 GND E5 TxIN16 E6 VCC E7 TxIN24 E8 GND F1 TxIN5 TxIN12 F5 TxIN17 ...
Page 15
Pin Descriptions (Continued) DS90CR286 MTD56 (TSSOP) Package Pin Description — Channel Link Receiver Pin Name I/O No. GND I 5 Ground pins for TTL outputs. PLL Power supply for PLL. CC PLL GND I 2 Ground pin ...
Page 16
Applications Information technologies such as PECL. Surface mount resistors are recommended to avoid the additional inductance that ac- companies leaded resistors. These resistors should be placed as close as possible to the receiver input pins to reduce stubs and effectively ...
Page 17
Applications Information FIGURE 21. Single-Ended and Differential Waveforms (Continued) 17 DS012910-26 www.national.com ...
Page 18
... Physical Dimensions 64 ball, 0.8mm fine pitch ball grid array (FBGA) package www.national.com inches (millimeters) unless otherwise noted Order Number DS90CR285MTD or DS90CR286MTD NS Package Number MTD56 Dimensions shown in millimeters only Order Number DS90CR285SLC NS Package Number SLC64A 18 ...
Page 19
... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...