HD64570F Renesas Electronics America, HD64570F Datasheet - Page 297

• Manufacturer Part Number: HD64570F
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register and Descriptor Setting: To start a memory-to-MSCI chained-block transfer, follow the
steps below starting with the DMA in its initial state. (Steps 1 to 6 may be completed in any
order.)
1.
2.
3.
4.
5.
6.
7.
External Bus Timing: In memory-to-MSCI chained-block transfer mode, one byte or one word
of data is transferred within one memory read cycle. The memory read cycle timing is the same as
that in memory-to-MSCI single-block transfer mode shown in figure 6.12.
Prior to the start of DMA transfer and at buffer switching, this transfer mode requires several set-
up cycles for the DMAC to perform a read operation on a descriptor and other operations, as
shown in figure 6.17. In the figure, 20 states (CPU modes 0, 2, and 3) or 32 states (CPU mode 1)
are inserted before the read operation of the transmit data. At buffer switching, one internal state
(in the middle of a frame) or five states (at the end of a frame) are inserted. (These states are
indicated by “*2” ) This is followed by a read operation of the next descriptor.
less), using the MPU. Note that since the high-order eight bits of the 24-bit address are
specified by CPB, the high-order eight bits are common to the same 64-Kbyte area. Specify a
16-bit chain pointer (CP), 24-bit buffer pointer (BP), 16-bit data length (DL), and the EOM
and EOT bits of ST in each descriptor. (Descriptors may be specified in DMA halt state.)
transfer.
next to the last transmit buffer into EDA.
Create any desired number of descriptors anywhere in the system memory area (64 Kbytes or
Set the TMOD bit of DMR to 1.
Clear the NF bit to 0 of DMR for single-frame transfer, and set the NF bit to 1 for multi-frame
Load the high-order eight bits of the 24-bit descriptor address into CPB.
Load the low-order 16 bits of the start address of the descriptor corresponding to the buffer
Load the start address of the descriptor corresponding to the first transmit buffer into CDA.
After steps 1 to 6, set the DE bit of DSR to 1 to start DMA operation.
Rev. 0, 07/98, page 281 of 453