LCMXO2-1200HC-C-EVN Lattice, LCMXO2-1200HC-C-EVN Datasheet - Page 8

• Manufacturer Part Number: LCMXO2-1200HC-C-EVN
• Description: KIT DEVELOPMENT MACHX02 PLD
• Manufacturer: Lattice
• Series: MachXO2r
• Type: PLDr

Specifications of LCMXO2-1200HC-C-EVN

• Contents: Board, Cable, Documentation, Power Supply
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: LCMXO2-1200HC-MG132CR1
• Other names: 220-1169

D
C
B
A
[14]
[14]
[14]
[14]
[14]
[14]
4MBit SPI
0_1uF
0_1uF
DI
DI
Micro SD Card Socket
uSD_CMD
C74
C74
5
uSD_DAT2
uSD_DAT3
uSD_CLK
uSD_DAT0
uSD_DAT1
5
VCC33
VCC33
uSD_DAT2
uSD_DAT3
uSD_CMD
uSD_CLK
uSD_DAT0
uSD_DAT1
8
7
3
4
8
7
3
4
Package: SOIC8 (WIDE)
Vcc
Reset
W
Vss
Vcc
Reset
W
Vss
U14
U14
AT25DF041A-SH-B
AT25DF041A-SH-B
U15
U15
AT25DF041A-MH-B
AT25DF041A-MH-B
Package: UDFN
Q
Q
S
C
D
S
C
D
1
6
5
2
1
6
5
2
1
2
3
5
7
8
microSD Socket
microSD Socket
U1
U1
DAT2
CD/DAT3
CMD
CLK
DAT0
DAT1
XO2_SPI_IN
XO2_SPI_OUT
XO2_SPI_IN
XO2_SPI_OUT
XO2_SPI_CS0
XO2_SPI_CLK
XO2_SPI_CS0
XO2_SPI_CLK
VDD
VSS
4
4
4
6
XO2_SPI_CS0 [14]
XO2_SPI_CLK [7,14]
XO2_SPI_IN
XO2_SPI_OUT [7,14]
VCC33
0_1uF
0_1uF
C81
C81
DI
DI
[7,14]
3
3
LPDDR - 128Mb (4 Meg x 4 banks x 8 data)
Empty External Pull-UP resistors. The internal XO2 resistors are used for bias.
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
[14]
0_001uF
0_001uF
C71
C71
LPDDR_A0
LPDDR_A1
LPDDR_A2
LPDDR_A3
LPDDR_A4
LPDDR_A5
LPDDR_A6
LPDDR_A7
LPDDR_A8
LPDDR_A9
LPDDR_A10
LPDDR_A11
LPDDR_A12
LPDDR_CK
LPDDR_CKn
LPDDR_CKE
LPDDR_CSn
LPDDR_RASn
LPDDR_CASn
LPDDR_BA0
LPDDR_BA1
LPDDR_WEn
DI
DI
0_01uF
0_01uF
C72
C72
DI
DI
LPDDR_A0
LPDDR_A1
LPDDR_A2
LPDDR_A3
LPDDR_A4
LPDDR_A5
LPDDR_A6
LPDDR_A7
LPDDR_A8
LPDDR_A9
LPDDR_A10
LPDDR_A11
LPDDR_A12
LPDDR_CK
LPDDR_CKn
LPDDR_CKE
LPDDR_CSn
LPDDR_RASn
LPDDR_CASn
LPDDR_BA0
LPDDR_BA1
LPDDR_WEn
LPDDR_DQ0
LPDDR_DQ1
LPDDR_DQ2
LPDDR_DQ3
LPDDR_DQ4
LPDDR_DQ5
LPDDR_DQ6
LPDDR_DQ7
0_1uF
0_1uF
R186
R186
0
0
DI
DI
C75
C75
DI
DI
RN2
RN2
0_1uF
0_1uF
C79
C79
2
2
K7
K8
K2
K3
H1
H2
H3
G2
G3
G1
H7
G9
G8
H8
H9
G7
D9
J8
J9
J1
J2
J3
J7
F7
F3
DI
DI
10
11
12
13
14
15
16
9
RN1_8_10K
RN1_8_10K
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CK
CK#
CKE
CS#
RAS#
CAS#
BA0
BA1
WE#
NC
NC
NC
Title
Title
Title
Size
Size
Size
Date:
Date:
Date:
8
7
6
5
4
3
2
1
B
B
B
DNI
DNI
VCC18
UDQS
LDQS
Memory LPDDR, SD, SPI
Memory LPDDR, SD, SPI
Memory LPDDR, SD, SPI
Document Number
Document Number
Document Number
MachXO2 Control Board
MachXO2 Control Board
MachXO2 Control Board
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
LDM
Tuesday, February 15, 2011
Tuesday, February 15, 2011
Tuesday, February 15, 2011
A8
B7
B8
C7
C8
D7
D8
E7
E3
D2
D3
C2
C3
B2
B3
A2
F2
E2
F8
E8
Lower Byte Mask & Strobe
MT46H16M16LFBF
MT46H16M16LFBF
VCC18
U6
U6
LPDDR_DQ0
LPDDR_DQ1
LPDDR_DQ2
LPDDR_DQ3
LPDDR_DQ4
LPDDR_DQ5
LPDDR_DQ6
LPDDR_DQ7
LPDDR_LDM
LPDDR_LDQS
RN3
RN3
R158
R158
R159
R159
10
11
12
13
14
15
16
9
RN1_8_10K
RN1_8_10K
10K
10K
10K
10K
LPDDR_DQ0 [14]
LPDDR_DQ1 [14]
LPDDR_DQ2 [14]
LPDDR_DQ3 [14]
LPDDR_DQ4 [14]
LPDDR_DQ5 [14]
LPDDR_DQ6 [14]
LPDDR_DQ7 [14]
LPDDR_LDM [14]
LPDDR_LDQS [14]
Sheet
Sheet
Sheet
8
7
6
5
4
3
2
1
DI
DI
DI
DI
DI
DI
1
1
VCC18
8
8
8
of
of
of
14
14
14
Rev
Rev
Rev
A
A
A
D
C
B
A