DK-SI-5SGXEA7/ES Altera, DK-SI-5SGXEA7/ES Datasheet
DK-SI-5SGXEA7/ES
Specifications of DK-SI-5SGXEA7/ES
Related parts for DK-SI-5SGXEA7/ES
DK-SI-5SGXEA7/ES Summary of contents
Page 1
... Stratix V User Guide Lite By Allan Davidson, Senior Product Manager, Altera Corporation ® Altera’s 28-nm Stratix V FPGAs deliver the highest bandwidth, highest levels of system integration and ultimate flexibility to the system designer. Featuring several new innovations, this FPGA family enables designers to meet demands for the constantly-growing high bandwidth needs across a broad variety of applications while meeting required cost and power budgets ...
Page 2
... Also common to Stratix V family variants is the new Embedded HardCopy Block (EHB) which is a customizable hard IP block that leverages Altera’s unique HardCopy ASIC capabilities. The EHB is used for hardening standard or logic intensive functions such as interface protocols, application-specific functions and proprietary custom IP ...
Page 3
... Altera Corporation Page 3 Stratix V Device Family User Guide Lite ...
Page 4
... Page 4 Figure 2. Altera’s new Embedded HardCopy Block in Stratix V FPGAs PCI Express Gen 3/2/1 Hard IP (EHB) The Stratix V devices have PCI Express hard IP designed for performance, ease-of-use and increased functionality. The PCI Express hard IP consists of the PCS, Data Link and Transaction layers. The PCI Express hard IP supports Gen 3/2/1 End Point and Root Port × ...
Page 5
... Then there are applications within the military, test and high-performance computing industries that push the envelope in terms of both performance and precision – sometimes even requiring the need for single/double precision floating point when implementing complex matrix operations and FFTs. Altera Corporation Page 5 Stratix V Device Family User Guide Lite ...
Page 6
... FFT algorithm. This algorithm has the characteristic of increasing precision requirements on only one side of the multiplier. The variable precision DSP block is designed to support this with proportional increase in DSP resources with precision growth. Altera Corporation Expected Usage Low precision fixed point ...
Page 7
... Variable Precision DSP Blocks Table 2. Complex Multiplication with Variable Precision DSP Blocks Additionally, for FFT applications with high dynamic range requirements, only the Altera FFT Megacore offers an option of single precision floating point implementation, with resource usage and performance similar to high precision fixed point implementations. ...
Page 8
... The transceivers are positioned on the outer edges of the chip as shown in Figure 6. They are isolated from the rest of the chip to prevent core and I/O noise from coupling into the transceivers; thereby ensuring optimal signal integrity. The transceiver channels consist of the Physical Medium Attachment Altera Corporation ® II embedded processor ...
Page 9
... This figure represents a given variant of a Stratix V device with transceivers. Other variants may have a different floorplan than the one shown here. (2) You can use the unused transceiver channels as additional transceiver transmit PLLs. Figure 6. Stratix V GT/GX/GST Device Chip View Altera Corporation Page 9 Stratix V Device Family User Guide Lite ...
Page 10
... On-chip instrumentation (EyeQ data-eye monitor) Dynamic reconfiguration Protocol support Table 3. Transceiver PMA Features Altera Corporation Capability 10GBase-KR, 14.1 Gbps (Stratix V GT/GX/GS devices) 10G Form-factor Pluggable (XFP), Small Form-factor Pluggable (SFP+), Quad Small Form-factor Pluggable (QSFP), CXP, 100G Pluggable (CFP), 100G Form- ...
Page 11
... FPGA. The hard FIFO also lowers PHY latency, resulting in higher random access performance. Third, the I/Os include on-chip dynamic termination to reduce the number of external components and minimize reflections. Altera Corporation Transmit Data Path Phase compensation FIFO, byte ...
Page 12
... Stratix V devices use an improved adaptive logic module (ALM) to implement logic functions more efficiently. The ALM shown in Figure 8 has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders and four dedicated registers. Altera Corporation Stratix V Device Family User Guide Lite ...
Page 13
... Clocking The Stratix V device core clock network is designed to support 717 MHz fabric operation and 1066 MHz/2133 Mbps external memory interfaces. The clock network architecture is based on Altera’s proven global, quadrant and peripheral clock structure which is supported by dedicated clock input pins and fractional clock synthesis PLLs ...
Page 14
... PowerPlay feature identifies critical timing paths in a design and biases core logic in that path for high performance (see Figure 10). The PowerPlay feature also identifies non-critical timing paths and biases core logic in that path for low power instead of high performance. PowerPlay monitors the slack of each Altera Corporation Stratix V Device Family User Guide Lite ...
Page 15
... CvP meets the PCI Express 100 ms power-up to active time requirement. Stratix V devices and the Quartus II software support partial reconfiguration through CvP, which reduces system downtime by keeping the PCI Express link alive while the FPGA is reconfigured. Altera Corporation Page 15 Stratix V Device Family User Guide Lite ...
Page 16
... Altera Corporation Remote Compression Encryption Update ...
Page 17
... Altera continues to dramatically improve the density and I/O performance of their FPGAs, and further strengthens its competitive position versus ASICs and ASSPs. From the core to the I/O, Altera is delivering innovations that provide higher system performance at lower cost and power. Stratix V FPGAs break through the bandwidth barrier. ...
Page 18
... Page 18 Features Summary 1066‐MHz/2133‐Mbps external memory interface Altera Corporation Stratix V Device Family User Guide Lite ...