SI4730-D60-GM Silicon Laboratories Inc, SI4730-D60-GM Datasheet
SI4730-D60-GM
Specifications of SI4730-D60-GM
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SI4730-D60-GM Summary of contents
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... 2.7~5 2.0~5.5 V (SSO Rev. 1.0 3/11 Si4730/31/34/35-D60 ADIO Multiplexed stereo audio AUXIN ADC with 85 dB dynamic range Seven selectable AM channel filters AM/FM/SW/LW digital tuning EN55020 compliant No manual alignment necessary Programmable reference clock Adjustable soft mute control ...
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... Si4730/31/34/35-D60 2 Rev. 1.0 ...
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... Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1. Si473x- .30 5.2. Si473x- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7. Package Markings (Top Marks 7.1. Si473x-D60 Top Mark (QFN 7.2. Top Mark Explanation (QFN 7.3. Si473x-D60 Top Mark (SSOP 7.4. Top Mark Explanation (SSOP Si4730/31/34/35-D60 Rev. 1.0 Page 3 ...
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... Si4730/31/34/35-D60 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.1. Si473x QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8.2. Si473x SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 9.1. Si473x QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 9.2. Si473x SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 4 Rev. 1.0 ...
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... The Si473x devices are high-performance RF integrated circuits with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. 3. For input pins DFS, SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, GPO3, and DCLK input pins FMI and AMI. Si4730/31/34/35-D60 1 Symbol Test Condition ...
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... Si4730/31/34/35-D60 Table 3. DC Characteristics (V = 2 1. Parameter FM Mode V Supply Current AQFN V Supply Current DQFN V Supply Current ASSOP V Supply Current DSSOP V Supply Current AQFN V Supply Current DQFN V Supply Current ASSOP V Supply Current DSSOP AM Mode V Supply Current AQFN V Supply Current DQFN ...
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... Backwards compatible mode to rev B and rev C. Additional features on this device may increase typical supply current. 3. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, GPO1, GPO2, and GPO3. 4. For output pins SDIO, DOUT, GPO1, GPO2, and GPO3. Si4730/31/34/35-D60 = – °C) Symbol ...
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... Si4730/31/34/35-D60 Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST ...
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... When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si473x delays SDIO by a minimum of 300 ns from the V specification. 5. The maximum t has only to be met when f HD:DAT violated as long as all other timing parameters are met. Si4730/31/34/35-D60 1,2,3 = – °C) Symbol Test Condition f SCL t ...
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... Si4730/31/34/35-D60 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev ...
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... SCLK 30 70% SEN 30% 70% SDIO A7 30% Figure 4. 3-Wire Control Interface Write Timing Parameters 70% SCLK 30 70% SEN 30% 70% SDIO A7 30% Figure 5. 3-Wire Control Interface Read Timing Parameters Si4730/31/34/35-D60 = – °C) Symbol Test Condition f CLK t HIGH t LOW HSDIO t HSEN t Read CDV t Read CDZ ...
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... Si4730/31/34/35-D60 Table 7. Digital Audio Interface Characteristics (V = 2 1. Parameter DCLK Cycle Time DCLK Pulse Width High DCLK Pulse Width Low DFS Set-up Time to DCLK Rising Edge DFS Hold Time from DCLK Rising Edge DOUT Propagation Delay from DCLK Falling ...
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... EMF – – > 2 MHz 10. kHz. 11. Sensitivity measured at (S+N)/ dB. 12. Blocker Amplitude = 100 dBmV. 13. At temperature (25 °C). Si4730/31/34/35-D60 1,2 = – °C) Symbol Test Condition f RF (S+N)/ kHz, RDS BLER < 0.3 ±200 kHz ±400 kHz In-band –3 dB –3 dB FM_DEEMPHASIS = 2 FM_DEEMPHASIS = 1 ...
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... Si4730/31/34/35-D60 Table 8. FM Receiver Characteristics (V = 2 1. Parameter 3,4,5,6,7,11,12 Intermod Sensitivity 7,11 Audio Output Load Resistance 7,11 Audio Output Load Capacitance 7 Seek/Tune Time 7 Powerup Time 12 RSSI Offset Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” ...
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... EMF 8. Analog output mode – – > 2 MHz 10. kHz. 11 and R pins. OUT OUT 12. At temperature (25 °C). Si4730/31/34/35-D60 = – °C) Symbol Test Condition f RF (S+N)/ 0.3 ±200 kHz ±400 kHz –3 dB –3 dB FM_DEEMPHASIS = 2 FM_DEEMPHASIS = 1 R Single-ended L C Single-ended L RCLK tolerance ...
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... Si4730/31/34/35-D60 Table 10. AM/SW/LW Receiver Characteristics (V = 2 1. Parameter Symbol Input Frequency 3,4,5 Sensitivity 5,6 Large Signal Voltage Handling 5 Power Supply Rejection Ratio 3,7 Audio Output Voltage 3,4,7 Audio S/N 3,7 Audio THD 5,8 Antenna Inductance 5 Powerup Time Notes: 1. Additional testing information is available in “AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure.” ...
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... Table 12. Digital Filter Characteristics—AUXIN Analog to Digital Converter (V = 2 1. Parameter Symbol Passband Frequency Response Passband Ripple Stopband Corner Frequency Stopband Attenuation Si4730/31/34/35-D60 = – °C) Test Condition THD kHz; measured 20 Hz—20 kHz SNR kHz at –60 dBFS A-weighted kHz at –60 dBFS non-weighted kHz with 3% Bandpass filter ...
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... Si4730/31/34/35-D60 Table 13. Reference Clock and Crystal Characteristics (V = 2 1. Parameter 1 RCLK Supported Frequencies 2 RCLK Frequency Tolerance REFCLK_PRESCALE REFCLK Crystal Oscillator Frequency 2 Crystal Frequency Tolerance Board Capacitance ESR CL–single ended Notes: 1. The Si473x divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. For more details, see Table 6 of “ ...
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... Layout, and Design Guidelines.” Silicon Laboratories will evaluate schematics and layouts for qualified customers. 5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface. 6. Place Si473x as close as possible to antenna and keep the FMI and AMI traces as short as possible. Si4730/31/34/35-D60 LIN RIN ...
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... Si4730/31/34/35-D60 2.2. SSOP Typical Application Schematic Notes: 1. Place C1 close to VA and C4 close to VD pin. 2. All grounds connect directly to GND plane on PCB. 3. Pins 6 and 7 are no connects, leave floating. 4. Pins 10 and 11 are unused. Tie these pins to GND ensure proper operation and receiver performance, follow the guidelines in “AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines.” ...
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... Resistor, 2 kΩ (Optional for digital audio) L2 Air Loop, 10-20 µH (Optional for AM Input) T1 Transformer, 1:5 turns ratio (Optional for AM Input) X1 32.768 kHz crystal (Optional for crystal oscillator option) Si4730/31/34/35-D60 Value/Description Optional Components Rev. 1.0 Supplier Murata Murata Murata Murata Jiaxin Silicon Laboratories ...
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... Si4730/31/34/35-D60 4. Functional Description 4.1. Overview RIN ANT LIN FMI AMI ANT RFGND 2.7~5.5 V VDD GND The Si473x-D60 CMOS AM/FM radio receiver IC integrates the complete tuner function from antenna input to audio output, including a stereo audio AUXIN ADC input for converting analog audio to digital signals. ...
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... Si4730/31/34/35-D60 4.4. AM Receiver The highly-integrated Si473x supports worldwide AM band reception from 520 to 1710 kHz using a digital low-IF architecture with a minimum number of external components and no manual alignment required. This ...
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... Si4730/31/34/35-D60 4.6. LW Receiver The Si4734/35 supports the long wave (LW) band from 153 to 279 kHz. The highly integrated Si4734/35 offers continuous digital tuning with components and no factory adjustments. The Si4734/35 also offers adjustable channel step sizes in 1 kHz increments, adjustable channel bandwidth settings, advanced seek algorithm, and soft mute ...
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... DFS DOUT 1 2 (OMODE = 1100) st (MSB at 1 rising edge) MSB 1 DCLK DOUT 1 nd (MSB at 2 rising edge) (OMODE = 1000) MSB Figure 10. DSP Digital Audio Format Si4730/31/34/35-D60 LEFT CHANNEL 1 DCLK n-2 3 n-1 n LSB 2 Figure Digital Audio Format LEFT CHANNEL 3 n-2 n MSB LSB ...
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... Si4730/31/34/35-D60 4.9. Stereo Audio Processing The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio kHz pilot tone, and RDS/RBDS data as shown in Figure 11 below ...
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... Refer to “AN332: Si47xx Programming Guide”. Si4730/31/34/35-D60 The Si473x uses RSSI, SNR, and AFC to qualify stations. Most of these variables have programmable thresholds for modifying the seek function according to customer needs ...
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... Si4730/31/34/35-D60 4.20. Control Interface A serial port slave interface is provided, which allows an external controller to send commands to the Si473x and receive responses from the device. The serial port can operate in two bus modes: 2-wire mode and 3-wire mode. The Si473x selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST ...
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... Table 3. This capability enables a much longer run time in battery operated devices. Si4730/31/34/35-D60 4.25. Programming with Commands To ease development time and offer maximum customization, the Si473x provides a simple yet powerful software interface to program the receiver. The device is programmed using commands, arguments, properties, and responses ...
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... Si4730/31/34/35-D60 5. Pin Descriptions 5.1. Si473x-GM RFGND Pin Number(s) Name connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 AMI AM RF input. AMI should be connected to the AM antenna. 5 Device reset input (active low). RST 6 Serial enable input (active low) ...
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... Analog supply voltage. May be connected directly to battery GND Ground. Connect to ground plane on PCB and bypass capacitor. 23 ROUT/[DOUT] Right audio line output in analog output mode. 24 LOUT/[DFS] Left audio line output in analog output mode. Si4730/31/34/35-D60 DOUT/[RIN LOUT/[DFS] ROUT/[DOUT] DFS/[LIN GPO3/[DCLK] 3 ...
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... Si4730/31/34/35-D60 6. Ordering Guide 1 Part Number Si4730-D60-GM AM/FM Broadcast Radio Receiver 2 Si4730-D60-GU Si4731-D60-GM AM/FM Broadcast Radio Receiver with 2 RDS/RBDS Si4731-D60-GU Si4734-D60-GM AM/FM/SW/LW Broadcast Radio Receiver 2 Si4734-D60-GU Si4735-D60-GM AM/FM/SW/LW Broadcast Radio Receiver 2 with RDS/RBDS Si4735-D60-GU Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. ...
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... Justified Year WW = Workweek Si4730/31/34/35-D60 3460 DTTT YWW YWW 30 = Si4730 Si4731 Si4734 Si4735 Firmware Revision 6. Revision D Die. Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 ...
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... Part Number Die Revision Line 1 Marking: Firmware Revision Package Type YY = Year WW = Work week Line 2 Marking: TTTTTT = Manufacturing code 34 473XD60GU YYWWTTTTTT 4730 = Si4730; 4731 = Si4731; 4734 = Si4734; 4735 = Si4735 Revision D die Firmware Revision 6. 24-pin SSOP Pb-free package Assigned by the Assembly House. Rev. 1.0 ...
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... D 3.00 BSC D2 1.65 1.70 e 0.50 BSC E 3.00 BSC E2 1.65 1.70 Notes: 1. All dimensions are shown in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. Si4730/31/34/35-D60 Table 16. Package Dimensions Symbol Max 0.60 f 0.05 L 0.30 L1 0.37 aaa bbb 1.75 ccc ddd eee 1 ...
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... Si4730/31/34/35-D60 8.2. Si473x SSOP Figure 13 illustrates the package details for the Si473x. Table 17 lists the values for the dimensions shown in the illustration. Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. ...
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... PCB Land Pattern 9.1. Si473x QFN Figure 14 illustrates the PCB land pattern details for the Si473x-D60-GM QFN. Table 18 lists the values for the dimensions shown in the illustration. Si4730/31/34/35-D60 Figure 14. PCB Land Pattern Rev. 1.0 37 ...
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... Si4730/31/34/35-D60 Table 18. PCB Land Pattern Dimensions Symbol Millimeters Min 2.10 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly No-Clean, Type-3 solder paste is recommended. 8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Si4730/31/34/35-D60 Figure 15. PCB Land Pattern Min 5.20 0.635 BSC ...
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... Si4730/31/34/35-D60 10. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references: EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure ...
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... N : OTES Si4730/31/34/35-D60 Rev. 1.0 41 ...
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... Si4730/31/34/35-D60 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...