SI4706-C30-GM Silicon Laboratories Inc, SI4706-C30-GM Datasheet
SI4706-C30-GM
Specifications of SI4706-C30-GM
Related parts for SI4706-C30-GM
SI4706-C30-GM Summary of contents
Page 1
... ERFORMANCE Note: The Si4706-C30 requires a patch for production operation. See section “11. Additional Reference Resources” Features Worldwide FM band support (76–108 MHz) Advanced patented RDS/RBDS decoding engine Outstanding RDS sensitivity Leading RDS synchronization metrics Highly reliable RDS decoder ...
Page 2
... Si4706-C30 2 Rev. 1.0 ...
Page 3
... Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. Pin Descriptions: Si4706- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1. Si4706 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9. Package Outline: Si4706 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. PCB Land Pattern: Si4706 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Si4706-C30 Rev. 1.0 Page 3 ...
Page 4
... Exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. The Si4706 device is a high-performance RF integrated circuit with certain pins having an ESD rating of < HBM. Handling and assembly of these devices should only be done at ESD-protected workstations. ...
Page 5
... Analog Output Mode DDPD I SCLK, RCLK inactive IOPD 500 µA 0 OUT –500 µA OL OUT Rev. 1.0 Si4706-C30 Min Typ Max Unit — 21 — 400 600 µA — — µA — 0 –0.3 — 0 –10 — 10 µA –10 — 10 — — IO — — ...
Page 6
... Si4706-C30 Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is high) does not occur within 300 ns before the rising edge of RST ...
Page 7
... RST. 3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until after the first start condition. 4. The Si4706 delays SDIO by a minimum of 300 ns from the V specification. 5. The maximum t ...
Page 8
... Si4706-C30 SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and Write Timing Diagram HIGH t r:IN f: HD:DAT SU:DAT D7-D0 ACK DATA ACK Rev ...
Page 9
... HSDIO HIGH LOW t S A6-A5, R/W, A0 D15 A4-A1 Address HSDIO CDV t S A6-A5, R/W, A0 D15 A4-A1 ½ Cycle Bus Address In Turnaround Rev. 1.0 Si4706-C30 Min Typ Max Unit 0 — 2.5 MHz 25 — — — — — — — — — — ...
Page 10
... Si4706-C30 Table 7. SPI Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to SCLKHold Hold SEN Input to SCLK to SDIO Output Valid SCLK ...
Page 11
... Figure 8. Digital Audio Interface Timing Parameters – °C) A Symbol Test Condition t DCT t DCH t DCL t SU:DFS t HD:DFS t PD:DOUT t DCL t DCT t HD:DFS PD:OUT Rev. 1.0 Si4706-C30 Min Typ Max 26 — 1000 10 — — 10 — — 5 — — 5 — — 0 — SU:DFS 2 S Mode ...
Page 12
... Procedure.” Volume = maximum for all tests. Tested 98.1 MHz ensure proper operation and receiver performance, follow the guidelines in “AN332: Si47xx Programming Guide”, “AN344: Si4706/07/4x Programming Guide”, and “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines”. Silicon Laboratories will evaluate schematics and layouts for qualified customers. ...
Page 13
... Procedure.” Volume = maximum for all tests. Tested 98.1 MHz ensure proper operation and receiver performance, follow the guidelines in “AN332: Si47xx Programming Guide”, “AN344: Si4706/07/4x Programming Guide”, and “AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines”. Silicon Laboratories will evaluate schematics and layouts for qualified customers. ...
Page 14
... Board Capacitance Notes: 1. Guaranteed by characterization. 2. The Si4706 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK frequencies between 31.130 kHz and 40 MHz that are not supported. See “AN332: Universal Programming Guide,” Table 6 for more details. ± frequency tolerance of 50 ppm is required for FM seek/tune using 50 kHz channel spacing ...
Page 15
... Layout and Design Guidelines”. Silicon Laboratories will evaluate schematics and layouts for qualified customers. 4. Pin 2 or Pin 4 connects to the FM antenna interface. Pin 2 is for a half-wave antenna. Pin 4 is for an embedded antenna. 5. Place Si4706 as close as possible to antenna jack and keep the FMI and LPI traces as short as possible. R1 ...
Page 16
... Si4706-C30 3. Bill of Materials Component(s) C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R U1 Si4706 FM Radio Receiver C2, C3 Crystal load capacitors, 22 pF, ±5%, COG (Optional: for crystal oscillator option) X1 32.768 kHz crystal (Optional: for crystal oscillator option) R1 Resistor, 2 k(Optional: for digital audio) R2 Resistor, 2 k ...
Page 17
... The Si4706 provides complete, decoded and error-corrected RDS groups (100 blocks groups at a time. The Si4706 offers several modes of operation for various applications which require more or less visibility to the RDS status and group data. *Note: The term “ ...
Page 18
... FM Receiver The Si4706 FM receiver is based on the proven Si4700/01/02/03 FM radio receiver. The part leverages Silicon Laboratories' proven and patented FM broadcast radio receiver digital architecture, delivering excellent RF performance and interference rejection ...
Page 19
... The Si4706-C30 defaults set RSSI to a mid- level threshold and add an SNR threshold set to a level delivering acceptable audio performance. This trade-off will eliminate very low RSSI stations whilst keeping the seek time to acceptable levels ...
Page 20
... Si4706-C30 4.11.1. Audio Data Formats The digital audio interface operates in slave mode and supports three different audio data formats Left-Justified DSP Mode mode, by default the MSB is captured on the second rising edge of DCLK following each DFS transition. The remaining bits of the word are sent in order, down to the LSB ...
Page 21
... S Digital Audio Format LEFT CHANNEL 3 n-2 n MSB LSB LEFT CHANNEL 3 n-2 n MSB LSB LEFT CHANNEL 2 3 n-2 n MSB LSB Rev. 1.0 Si4706-C30 RIGHT CHANNEL n-2 n MSB LSB RIGHT CHANNEL 2 3 n-2 n-1 n LSB RIGHT CHANNEL 3 n-2 n-1 n LSB RIGHT CHANNEL 2 3 n-2 n-1 ...
Page 22
... Si4706-C30 4.12. Embedded Antenna Support The Si4706 is the first FM receiver to support the fast growing trend to integrate the FM receiver antenna into the device enclosure. The chip is designed with this function in mind from the outset, with multiple international patents pending, thus it is superior to many other options in price, board space, and performance ...
Page 23
... Re-synchronization time in typical RDS decoder using hard decision techniques. CNR Level at which typical RDS decoder returns block error and declares sync loss. Figure 15. Illustrative Si4706 Advanced RDS Synchronization Decoder Failure Probability 1.E+00 1.E-01 1.E-02 RDS Standard Limits 1.E-03 Si4706 RDS Decoder 1 ...
Page 24
... The serial port can operate in three bus modes: 2-wire mode, 3-wire mode, or SPI mode. The Si4706 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST. The GPO1 pin includes an internal ...
Page 25
... SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the Si4706 will drive the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK. A transaction ends when the user sets SEN high, then pulses SCLK high and low one final time ...
Page 26
... All commands provide a one-byte status update indicating interrupt and clear-to-send status information. For a detailed description of the commands and properties for the Si4706, see “AN332: Si47xx Programming Guide” and “AN344: Si4706/07/4x Programming Guide.” Rev. 1.0 Programming ...
Page 27
... Commands and Properties Refer to “AN332: Si47xx Programming Guide” and “AN344: Si4706/07/4x Programming Guide.” Si4706-C30 Rev. 1.0 27 ...
Page 28
... Si4706-C30 6. Pin Descriptions: Si4706-GM RFGND Pin Number(s) Name FMI 3 RFGND 4 LPI 5 RST 6 SEN 7 SCLK 8 SDIO 9 RCLK ROUT 14 LOUT 15 DOUT 16 DFS 17 GPO3/DCLK 18 GPO2/INT 19 GPO1 12, GND PAD GND FMI 2 15 DOUT 3 14 GND PAD LPI 4 13 RST Description No connect. Leave floating input. RF ground. Connect to ground plane on PCB. ...
Page 29
... Ordering Guide Part Number* Si4706-C30-GM FM RDS Broadcast Radio Receiver *Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel. Description Rev. 1.0 Si4706-C30 Package Operating Type Temperature QFN – °C Pb-free 29 ...
Page 30
... Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Workweek 30 0630 CTTT YWW Figure 17. Si4706 Top Mark 06 = Si4706 30 = Firmware Revision Revision C Die Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date. Rev. 1.0 ...
Page 31
... Package Outline: Si4706 QFN Figure 18 illustrates the package details for the Si4706. Table 12 lists the values for the dimensions shown in the illustration. Figure 18. 20-pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.50 0.55 A1 0.00 0.02 b 0.18 0.25 c 0.27 0.32 D 3.00 BSC D2 1 ...
Page 32
... Si4706-C30 10. PCB Land Pattern: Si4706 QFN Figure 19 illustrates the PCB land pattern details for the Si4706-GM. Table 13 lists the values for the dimensions shown in the illustration. 32 Figure 19. PCB Land Pattern Rev. 1.0 ...
Page 33
... A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Notes: Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for small body components. Si4706-C30 Symbol Millimeters Min GE 2.10 W — ...
Page 34
... To request access, register at http://www.silabs.com and send user’s first and last name and company name to FMinfo@silabs.com. AN332: Si47xx Programming Guide AN342: Quick Start Guide AN344: Si4706/07/4x Programming Guide AN383: Si47xx Antenna, Schematic, Layout and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure ...
Page 35
... N : OTES Si4706-C30 Rev. 1.0 35 ...
Page 36
... Si4706-C30 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...