ADN4605ABPZ Analog Devices Inc, ADN4605ABPZ Datasheet
ADN4605ABPZ
Specifications of ADN4605ABPZ
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ADN4605ABPZ Summary of contents
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FEATURES DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization 3 dB boost Compensates over 40 inches of FR4 at 4.25 Gbps Adjustable transmit preemphasis/deemphasis Programmable boost and output level Compensates over ...
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ADN4605 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Specifications............................................................... Timing Specifications............................................................ 5 SPI Timing Specifications ........................................................... 5 Parallel Mode ...
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SPECIFICATIONS ELECTRICAL SPECIFICATIONS TTIx TTOx equalizer (EQ dB), data rate = 4.25 Gbps (PRBS7 data pattern), ac-coupled inputs and outputs, differential input swing ...
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ADN4605 Parameter Conditions Supply Current All outputs enabled, ac-coupled I/O, 200 mV I/O swings (400 mV p-p differential boost = 0 dB, 50 Ω far-end terminations I DVCC TTIA TTIB TTOA ...
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I C TIMING SPECIFICATIONS SDA LOW SCL t HD;STA t HD;DAT S 2 Table Timing Specifications Parameter SCL Clock Frequency Hold Time for a Start Condition Setup Time for a Repeated ...
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ADN4605 PARALLEL MODE SPECIFICATIONS D7:D0 A7: UPDATE 0 Table 4. Parallel Mode Write Cycle Timing Specifications Parameter Chip Select Setup Time Parallel Data ...
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ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Rating 3 3 TTIA TTIB TTOA TTOB CC 1 Internal Power Dissipation 8.4 ...
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ADN4605 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ON39 OP39 ON37 OP37 ON35 OP35 ON33 OP33 ON31 OP31 ON29 OP29 ON27 OP27 ON25 OP25 ON23 OP23 ON21 OP21 ...
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Table 7. Pin Function Descriptions Pin No. Mnemonic ON39 A5 OP39 A6 ON37 A7 OP37 A8 ON35 A9 OP35 A10 ON33 A11 OP33 A12 ON31 A13 OP31 A14 ON29 A15 ...
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ADN4605 Pin No. Mnemonic B23 ON20 B24 OP20 B25 V EE B26 IP0 TTOB C8 V TTOB C9 V TTOB ...
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Pin No. Mnemonic D13 V EE D14 V EE D15 V EE D16 V CC D17 V CC D18 V EE D19 V EE D20 V EE D21 V EE D22 V CC D23 DV CC D24 V CC D25 ...
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ADN4605 Pin No. Mnemonic H25 IP36 H26 IN35 J1 IN5 J2 IP6 J3 V TTIA C/SPI/UPDATE J23 RE/SDI J24 V TTIB J25 IN34 J26 IP35 K1 IP7 K2 IN6 SER/ PAR K23 CS ...
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Pin No. Mnemonic N23 DATA2 N24 V TTIB N25 IN30 N26 IP31 P1 IP11 P2 IN10 P3 V TTIA P4 ADDR2 P23 DATA3 P24 V TTIB P25 IP30 P26 IN29 R1 IN11 R2 IP12 ADDR3 R23 ...
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ADN4605 Pin No. Mnemonic V24 V TTIB V25 IP26 V26 IN25 W1 IN15 W2 IP16 W3 V TTIA W4 ADDR7 W23 V EE W24 V TTIB W25 IN24 W26 IP25 Y1 IP17 Y2 IN16 Y3 V TTIA ...
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Pin No. Mnemonic AC11 V CC AC12 V CC AC13 V EE AC14 V EE AC15 V EE AC16 V CC AC17 V CC AC18 V EE AC19 V EE AC20 V EE AC21 V EE AC22 V CC AC23 ...
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ADN4605 Pin No. Mnemonic AE1 V EE AE2 V EE AE3 OP0 AE4 ON0 AE5 OP2 AE6 ON2 AE7 OP4 AE8 ON4 AE9 OP6 AE10 ON6 AE11 OP8 AE12 ON8 AE13 OP10 AE14 ON10 AE15 OP12 AE16 ON12 AE17 OP14 ...
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Pin No. Mnemonic AF23 ON19 AF24 V EE AF25 V EE AF26 V EE Type Description Output High Speed Output Complement. Power Negative Supply. Power Negative Supply. Power Negative Supply. Rev Page ADN4605 ...
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ADN4605 TYPICAL PERFORMANCE CHARACTERISTICS TTIx TTOx equalizer (EQ dB), data rate = 4.25 Gbps (PRBS7 data pattern), ac-coupled inputs and outputs, differential input ...
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CABLES 2 2 DATA OUT FR4 TEST BACKPLANE DIFFERENTIAL PATTERN STRIPLINE TRACES GENERATOR TP1 8mils WIDE, 8mils SPACE, 8mils DIELECTRIC HEIGHT LENGTHS = 10 INCHES, 20 INCHES, 30 INCHES, 40 INCHES 0.167UI/DIV Figure 13. 4.25 Gbps Input Eye, 20 ...
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ADN4605 50Ω CABLES 2 DATA OUT PATTERN GENERATOR 0.167UI/DIV Figure 18. 4.25 Gbps Output Eye, 20-Inch FR4 Output Channel (TP3 from Figure 17) 0.167UI/DIV Figure 19. 4.25 Gbps Output Eye, 40-Inch FR4 Input Channel ...
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DATA RATE (Gbps) Figure 22. Deterministic Jitter vs. Data Rate 100 2.25 2.50 2.75 3.00 3.25 SUPPLY VOLTAGE (V) Figure 23. Deterministic Jitter vs. Supply ...
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ADN4605 3dB EQ = 6dB EQ = 12dB INPUT FR4 TRACE LENGTH (Inches) Figure 28. Deterministic Jitter vs. Input FR4 Channel Length 100 ...
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TEMPERATURE (°C) Figure 34. Rise/Fall Time vs. Temperature 1200 1150 1100 1050 1000 950 900 850 800 2.375 2.500 3.300 SUPPLY VOLTAGE (V) Figure 35. Propagation ...
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ADN4605 THEORY OF OPERATION INTRODUCTION The ADN4605 × 40, buffered, asynchronous crosspoint switch that provides input equalization, output preemphasis, and output level programming capabilities. The receivers integrate an equalizer that is optimized to compensate for typical backplane ...
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RECEIVERS Input Structure and Input Levels The ADN4605 receiver inputs incorporate 50 Ω termination resistors, ESD protection, and a fixed equalizer that is optimized for operation over long backplane traces. Each receive channel also provides a positive/negative (P/N) inversion function, ...
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ADN4605 Register Address Default Register Name 0xC7 0x0 Rx EQ Control ( 28) 0xC8 0x0 Rx EQ Control (Rx IN35 32) 0xC9 0x0 Rx EQ Control ( ...
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SWITCH CORE The ADN4605 switch core is a fully nonblocking 40 × 40 array that allows multicast and broadcast configurations. The config- uration of the switch core is programmed through either the serial or parallel control interface. The crosspoint configuration ...
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ADN4605 Table 11. XPT Control Registers Register Address Default Register Name 0x00 0x00 Software Reset (Write only) 0x01 0x00 XPT Update (Write only) 0x02 0x00 XPT Map Table Select 0x03 0x00 XPT Broadcast (Write only) 0x04 to 0x2B 0x00 to ...
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TRANSMITTERS Output Structure and Output Levels The ADN4605 transmitter outputs incorporate 50 Ω termin- ation resistors, ESD protection, and output current switches. Each channel provides independent control of both the absolute output level and the preemphasis output level. Note that ...
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ADN4605 Table 13. Transmitter Output Enable State Settings Register Address Default Register Name 0xB0 0x00 Tx Drive Control Tx3 to Tx0 0xB1 0x00 Tx Drive Control Tx7 to Tx4 0xB2 0x00 Tx Drive Control Tx11 to Tx8 0xB3 0x00 Tx ...
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The amount of high frequency boost provided by the transmit- ter is determined by both the output and preemphasis level settings. Table 14 provides an example of how the absolute output and preemphasis level settings determine the amount of high ...
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ADN4605 TERMINATION The inputs and outputs include integrated 50 Ω termination resistors. The internal resistors can be disabled for applications that require external termination resistors. For example, disabling the integrated 50 Ω termination resistors allow alternative termination values such as ...
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I C SERIAL CONTROL INTERFACE The ADN4605 register set is controlled through a 2-wire serial interface, both the SER/ PAR interface. To access the SPI lines must be held at logic high. The ...
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ADN4605 DATA READ To read data from the ADN4605 register set, a microcontroller any other I C master needs to send the appropriate control signals to the ADN4605 slave device. The steps are listed below; ...
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SPI SERIAL CONTROL INTERFACE The SPI serial interface of the ADN4605 CS , SCK, SDI, and SDO. In order to access the SPI interface the SER/ PAR line must be held at logic high and the I must be held ...
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ADN4605 CS 1 SCK SDI SDO START WRITE COMMAND Figure 48. SPI–Writing to the Address Pointer Register Followed by a Single Byte of Data to the Selected Register ...
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CS 1 SCK SDI SDO START READ COMMAND CS (CONTINUED) SCK (CONTINUED) SDI (CONTINUED) SDO (CONTINUED) Figure 49. SPI–Reading a Single Byte of Data from a Selected Register ...
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ADN4605 PARALLEL CONTROL INTERFACE The parallel control interface of the ADN4605 nineteen wires: ADDR[7:0], DATA[7:0 and access the parallel control interface, the SER/ PAR line must be held at logic low. The CS ...
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REGISTER MAP In the Register Map, when settings are provided in the Description column for the first bit, note that these settings apply to all bits with the same function. Table 19. Register Map Address: Channel Default Register Name 0x00 ...
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ADN4605 Address: Channel Default Register Name 0x2C 0x27 XPT Map 1 Control 0 0x2D 0x26 XPT Map 1 Control 1 0x2E 0x25 XPT Map 1 Control 2 0x2F 0x24 XPT Map 1 Control 3 0x30 0x23 XPT Map 1 Control ...
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Address: Channel Default Register Name 0x61 0x00 XPT Status 13 0x62 0x00 XPT Status 14 0x63 0x00 XPT Status 15 0x64 0x00 XPT Status 16 0x65 0x00 XPT Status 17 0x66 0x00 XPT Status 18 0x67 0x00 XPT Status 19 ...
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ADN4605 Address: Channel Default Register Name 0x99: Output 25 0x40 Tx Lane Control 0x9A: Output 26 0x40 Tx Lane Control 0x9B: Output 27 0x40 Tx Lane Control 0x9C: Output 28 0x40 Tx Lane Control 0x9D: Output 29 0x40 Tx Lane ...
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Address: Channel Default Register Name 0xAD 0x0 Tx Sign Control 0xB0 0x0 Tx Drive Control 0xB1 0x0 Tx Drive Control 0xB2 0x0 Tx Drive Control 0xB3 0x0 Tx Drive Control 0xB4 0x0 Tx Drive Control Bits Bit Name Description 7 ...
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ADN4605 Address: Channel Default Register Name 0xB5 0x0 Tx Drive Control 0xB6 0x0 Tx Drive Control 0xB7 0x0 Tx Drive Control 0xB8 0x0 Tx Drive Control 0xB9 0x0 Tx Drive Control 0xBA Write Only Tx Drive Control 0xBB 0x0 Tx ...
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Address: Channel Default Register Name 0xBC 0x0 Tx Termination Control 0xBD 0x0 Tx Termination Control 0xC0 0x0 Rx EQ Control 0xC1 0x0 Rx EQ Control 0xC2 0x0 Rx EQ Control 0xC3 0x0 Rx EQ Control Bits Bit Name Description 4 ...
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ADN4605 Address: Channel Default Register Name 0xC4 0x0 Rx EQ Control 0xC5 0x0 Rx EQ Control 0xC6 0x0 Rx EQ Control 0xC7 0x0 Rx EQ Control 0xC8 0x0 Rx EQ Control 0xC9 0x0 Rx EQ Control 0xCA 0x0 Rx EQ ...
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Address: Channel Default Register Name 0xCB 0x0 Rx Sign Control 0xCC 0x0 Rx Sign Control 0xCD 0x0 Rx Sign Control 0xCE 0x0 Rx Sign Control 0xCF 0x0 Rx Sign Control 0xD0 0x0 Rx Termination Control Bits Bit Name Description 7 ...
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ADN4605 Address: Channel Default Register Name 0xD1 0x0 Rx Termination Control Bits Bit Name Description 4 RXB_TERM [39:36] Input [39:36] (B Side) termination control 0: terminations enabled 1: terminations disabled 3 RXB_TERM [35:32] Input [35:32] (B Side) termination control 2 ...
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APPLICATIONS INFORMATION The ADN4605 is an asynchronous and protocol agnostic digital switch and, therefore, is applicable to a wide range of applica- tions including network routing and digital video switching. The ADN4605 supports the data rates and signaling levels of ...
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ADN4605 O/E O/E O/E ASIC 1 LOSSY CHANNEL IN 1 OUT OUT 2 ADN4605 40 × 40 CROSSPOINT SWITCH IN 39 OUT 39 Figure 51. ADN4605 Networking Switch Application Block Diagram 8 LANE UPLINK PATH Z 0 ...
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SUPPLY SEQUENCING Ideally, all power supplies should be brought up to the appropri- ate levels simultaneously (power supply requirements are set by the supply limits in Table 1 and the absolute maximum ratings listed in Table 6). If the power ...
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ADN4605 Example 3 2 TTOx In a typical application, the user can select a default output level of 200 mV single-ended (400 mVp-p differential) and may want the option to choose preemphasis settings ...
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CML Table 20. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting Single-Ended Output Levels and Tx Lane Control PE Boost Register Settings Boost PE SW-DC SW-PE (mV) (mV) % ...
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ADN4605 PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES The high speed differential inputs and outputs should be routed with 100 Ω controlled impedance differential transmission lines. The transmission lines, either microstrip or stripline, should be referenced to a solid low impedance ...
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... ADN4605 OUTLINE DIMENSIONS 35.10 35.00 SQ 34.90 BALL A1 INDICATOR TOP VIEW DETAIL A ORDERING GUIDE 1 Model Temperature Range ADN4605ABPZ −40°C to +85°C ADN4605-EVALZ RoHS Compliant Part 31.85 31.75 SQ 31.65 1.27 BSC DETAIL A 1.70 MAX 0.20 MIN 0.90 0.75 0.60 0.25 MIN BALL DIAMETER ...
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ADN4605 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and ...