SI5374B-A-GL Silicon Laboratories Inc, SI5374B-A-GL Datasheet
SI5374B-A-GL
Specifications of SI5374B-A-GL
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SI5374B-A-GL Summary of contents
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REQUENCY M /J ULTIPLIER Features Highly-integrated, 4 PLL clock multiplier/jitter attenuator Four independent DSPLLs support any-frequency synthesis and jitter attenuation 8 inputs/8 outputs Each DSPLL can generate ...
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Si5374 Functional Block Diagram Input Stage PLL Bypass CKIN1P_A ÷ N31 CKIN1N_A Monitor CKIN2P_A Hitless Switch CKIN2N_A ÷ N32 Internal Osc PLL Bypass CKIN3P_B ÷ N31 CKIN3N_B Monitor CKIN4P_B Hitless Switch CKIN4N_B ÷ N32 Internal Osc PLL Bypass CKIN5P_C ÷ ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5374 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature T A Supply Voltage during V DD Normal Operation Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply ...
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Table 2. DC Characteristics (V = 1.8 ± 5%, 2.5 ±10 – ° Parameter Symbol 1 Supply Current CKINn Input Pins Input Common Mode V ICM Voltage (Input Thresh- old Voltage) ...
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Si5374 Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10 – ° Parameter Symbol Single Ended Output CKO VSE Swing Differential Output CKO VD Voltage Common Mode Output CKO VCM Voltage ...
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Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10 – ° Parameter Symbol 2-Level LVCMOS Input Pins Input Voltage Low V IL Input Voltage High V IH LVCMOS Output Pins Output ...
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Si5374 Table 3. AC Characteristics (V = 1.8 ± 5%, 2.5 ±10 – ° Parameter Symbol Single-Ended Reference Clock Input Pin OSC_P (OSC_N with cap to GND) OSC_P to OSC_N OSC RIN Resistance Input ...
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Table 3. AC Characteristics (Continued 1.8 ± 5%, 2.5 ±10 – ° Parameter Symbol Output Rise/Fall CKO TRF (20–80%) @ 212.5 MHz output Output Duty Cycle CKO DC Uncertainty @ 622.08 MHz ...
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Si5374 Table 4. Microprocessor Control (V = 1.8 ± 5%, 2.5 ±10 – ° Symbol Parameter Bus Lines (SDA, SCL) Input Voltage Low VIL I2C Input Voltage High VIH I2C Input ...
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Table 5. Performance Specifications V = 1.8 V ±5% or2.5 V ±10 – ° Parameter Symbol 1 PLL Performance Lock Time t LOCKMP Output Clock Phase Change t P_STEP Closed Loop Jitter Peaking Jitter ...
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Si5374 Table 5. Performance Specifications (Continued 1.8 V ±5% or2.5 V ±10 – ° Parameter Symbol 2,3 Thermal Characteristics Maximum Junction 4 Temperature Thermal Resistance Junction to Ambient Thermal Resistance Junction to ...
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Typical Application Schematic FPGA 10G 10G PHY 10G IEEE PHY PHY 1588 Slave 1588 Recovered Clocks 4-Port 10G Line Card with SyncE and IEEE1588 Independent Port Timing Ethernet Datapath 4 10G PHY 4 Rx SyncE Recovered Clocks Si5374 SyncE_1 ...
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Si5374 3. Functional Description CKIN1P_A CKIN1N_A CKIN2P_A CKIN2N_A Internal Osc CKIN3P_B CKIN3N_B CKIN4P_B CKIN4N_B Internal Osc CKIN5P_C CKIN5N_C CKIN6P_C CKIN6N_C Internal Osc CKIN7P_D CKIN7N_D CKIN8P_D CKIN8N_D Internal Osc RSTL_q CS_CA_q SCL The Si5374 is a highly integrated jitter-attenuating clock multiplier ...
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Frequency Precision Clocks Family Reference Manual. Preliminary Rev. 0.4 Si5374 15 ...
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Si5374 4. Register Map The Si5374 has four identical register maps for each DSPLL. Each DSPLL has a unique I independent control and device configuration. The I corresponding DSPLL [A1] [A0] address is fixed as below. [A1] [A0] DSPLLA: 0 ...
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Reg N2_HS[2: 128 129 130 DIGHOLD VALID 131 132 134 135 PARTNUM_RO[3:0] 136 RST_REG ICAL 137 138 139 LOS2_EN[0: 142 143 185 Table ...
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Si5374 5. Register Descriptions Register 0. Bit D7 D6 FREE_RUN CKOUT_ALWAYS_ON Name R R/W Type Reset value = 0001 0100 Bit Name 7 Reserved 6 FREE_RUN Free Run. Internal to the device, route XA/XB to CKIN2. This allows the DSPLL ...
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Register 1. Bit D7 D6 Name R Type Reset value = 1110 0100 Bit Name 7:4 Reserved 3:2 CK_PRIOR2 2nd Priority Input Clock. [1:0] Selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: ...
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Si5374 Register 2. Bit D7 D6 BWSEL_REG [3:0] Name R/W Type Reset value = 0100 0010 Bit Name 7:4 BWSEL_REG [3:0] BWSEL_REG. Selects nominal f3dB bandwidth for PLL. See DSPLLsim for settings. After BWSEL_REG is written with a new value, ...
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Register 3. Bit D7 D6 CKSEL_REG[1:0] Name R/W Type Reset value = 0000 0101 Bit Name 7:6 CKSEL_REG CKSEL_REG. [1:0] If the device is operating in register-based manual clock selection mode (AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these ...
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Si5374 Register 4. Bit D7 D6 AUTOSEL_REG [1:0] Name R/W Type Reset value = 0001 0010 Bit Name 7:6 AUTOSEL_ AUTOSEL_REG [1:0]. REG [1:0] Selects input clock selection control method. 00: Manual (either register or pin controlled, see CKSEL_PIN) 01: ...
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Register 6. Bit D7 D6 Name R R Type Reset value = 0010 1101 Bit Name 7:6 Reserved 5:3 SFOUT2_ SFOUT2_REG [2:0]. REG [2:0] Controls output signal format and disable for CKOUT2 output buffer. 000: Reserved 001: Disable CKOUT2 010: ...
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Si5374 Register 7. Bit D7 D6 Name R R Type Reset value = 0010 1010 Bit Name 7:3 Reserved 2:0 FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for Frequency offset (FOS) monitoring. 000: ...
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Register 8. Bit D7 D6 HLOG_2[1:0] Name R/W Type Reset value = 0000 0000 Bit Name 7:6 HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur ...
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Si5374 Register 10. Bit D7 D6 Name R R Type Reset value = 0000 0000 Bit Name 7:4 Reserved 3 DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the NC2 output ...
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Register 19. Bit D7 D6 FOS_EN FOS_THR [1:0] Name R/W R/W Type Reset value = 0010 1100 Bit Name 7:5 FOS_EN FOS_EN. Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSX_EN, register 139). 0: FOS disable 1: ...
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Si5374 Register 20. Bit Name Type Reset value = 0011 1110 Bit Name 7:4 Reserved 3:2 Write 0 Write to zero. 1 LOL_PIN LOL_PIN. The LOL_INT status bit can be reflected on the LOL ...
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Register 21. Bit D7 D6 Write 0 Write 0 Name W W Type Reset value = 1111 1111 Bit Name 7:6 Write 0 Write zero. 5:2 Reserved 1 CK1_ACTV_PIN CK1_ACTV_PIN. The CK1_ACTV_REG status bit can be reflected to the CS_CA ...
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Si5374 Register 22. Bit Name Type Reset value = 1101 1111 Bit Name 7:4 Reserved 3 CK_ACTV_ POL CK_ACTV_POL. Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: ...
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Register 23. Bit Name Type Reset value = 0001 1111 Bit Name 7:3 Reserved 2 LOS2_MSK LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to ...
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Si5374 Register 24. Bit D7 D6 Name R R Type Reset value = 0011 1111 Bit Name 7:3 Reserved 2 FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg- ister do ...
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Register 25. Bit D7 D6 N1_HS [2:0] Name R/W Type Reset value = 0010 0000 Bit Name 7:5 N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS ( low-speed divider. 000: ...
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Si5374 Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = ...
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Register 34. Bit D7 D6 Name R R Type Reset value = 0000 0000 Bit Name 7:4 Reserved 3:0 NC2_LS NC2_LS [19:16]. [19:16] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000=1 00000000000000000001=2 ...
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Si5374 Register 36. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = ...
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Register 40. Bit D7 D6 N2_HS [2:0] Name R/W Type Reset value = 1100 0000 Bit Name 7:5 N2_HS [2:0] N2_HS [2:0]. Sets value for N2 high speed divider which drives N2LS low-speed divider. 000: 4 001: 5 010: 6 ...
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Si5374 Register 41. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... ...
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Register 43. Bit D7 D6 Name R R Type Reset value = 0000 0000 Bit Name 7:3 Reserved 2:0 N31 [18:16] N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... ...
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Si5374 Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider ...
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Register 47. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] N32_[15:8]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2 Valid divider values ...
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Si5374 Register 55. Bit D7 D6 Name R R Type Reset value = 0000 0000 Bit Name 7:6 Reserved 5:3 CLKIN2RATE[2:0] CLKIN2RATE_[2:0]. CKINn frequency selection for FOS alarm monitoring. 000: 10–27 MHz 001: 25–54 MHz 002: 50–105 MHz 003: 95–215 ...
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Register 128. Bit Name Type Reset value = 0010 0000 Bit Name 7:2 Reserved 1 CK2_ACTV_REG CK2_ACTV_REG. Indicates if CKIN2 is currently the active clock for the DSPLL input. 0: CKIN2 is not the ...
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Si5374 Register 130. Bit D7 D6 DIGHOLDVALID Name R R Type Reset value = 0000 0001 Bit Name 7 Reserved 6 DIGHOLDVALID Digital Hold Valid. Indicates if the digital hold circuit has enough samples of a valid clock to meet ...
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Register 131. Bit D7 D6 Name R R Type Reset value = 0001 1111 Bit Name 7:3 Reserved 2 LOS2_FLG CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is ...
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Si5374 Register 132. Bit D7 D6 Name R R Type Reset value = 0000 0010 Bit Name 7:4 Reserved 3 FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if output interrupt ...
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Register 134. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:0 PARTNUM_RO [11:0] Device 2). 0000 0100 1010: Si5374 Others: Reserved Register 135. Bit D7 D6 PARTNUM_RO [3:0] Name R Type Reset value ...
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Si5374 Register 136. Bit D7 D6 Name RST_REG ICAL R/W R/W Type Reset value = 0000 0000 Bit Name 7 RST_REG Internal Reset (Same as Pin Reset). Note: The I 0: Normal operation. 1: Reset all internal logic. Outputs disabled ...
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Register 138. Bit Name Type Reset value = 0000 1111 Bit Name 7:2 Reserved 1 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split between two ...
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Si5374 Register 139. Bit D7 D6 LOS2_EN [0:0] Name R R R/W Type Reset value = 1111 1111 Bit Name 7:6 Reserved 5 LOS2_EN [1:0] Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). Note: LOS2_EN is split ...
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Register 142. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPENDENTSKEW1 [7:0] Register 143. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPENDENTSKEW2 [7:0] INDEPENDENTSKEW2. Register 185. Bit D7 D6 ...
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Si5374 5.1. ICAL The device registers must be configured for the device operation. After device configuration, a calibration procedure must be performed once a stable clock is applied to the selected CKINn input. The calibration process is triggered by writing ...
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Pin Descriptions: Si5374 CKOUT1P_B GND VDD_B CKOUT1N_B GND CKIN1P_B GND GND CKIN2P_B CKOUT2N_B IRQ_B VDD_B LOL_C VDD_C CKOUT2P_B CS_CA_C CKIN1N_C CKIN2N_C VDD_C CKIN1P_C CKIN2P_C GND GND GND CKOUT1P_C CKOUT1N_C GND Figure 4. Si5374 Pin Configuration (Bottom ...
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Si5374 Pin # Pin Name I/O D4 RSTL_A I D6 RSTL_B F6 RSTL_C F4 RSTL_D B4 IRQ_A O D8 IRQ_B H6 IRQ_C F2 IRQ_D C1, C4, B5 VDD_A V DD A7, D5, D7 VDD_B E7, F5, G9 VDD_C E3, F3, ...
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Table 9. Si5374 Pin Descriptions (Continued) Pin # Pin Name I/O B2 GND GND A3 GND B3 GND E4 GND C8 GND A8 GND B8 GND C9 GND H7 GND J7 GND H8 GND H9 GND G1 GND H2 GND ...
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Si5374 Table 9. Si5374 Pin Descriptions (Continued) Pin # Pin Name I/O D1 CS_CA_A I/O A6 CS_CA_B F9 CS_CA_C J4 CS_CA_D G5 SCL I G6 SDA I/O Note: Internal register names are indicated by italics, e.g., IRQ_PIN . See Si5374 ...
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Table 9. Si5374 Pin Descriptions (Continued) Pin # Pin Name I/O B1 CKOUT1P_A O A2 CKOUT1N_A A5 CKOUT2P_A A4 CKOUT2N_A A9 CKOUT1P_B B9 CKOUT1N_B E9 CKOUT2P_B D9 CKOUT2N_B J9 CKOUT1P_C J8 CKOUT1N_C J5 CKOUT2P_C J6 CKOUT2N_C J1 CKOUT1P_D H1 CKOUT1N_D ...
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... Si5374 7. Ordering Guide Ordering Part Input/Output Number Clocks Si5374B-A-GL 8/8 Si5374-EVB 58 PLL Package Bandwidth Range 4 to 525 Hz 10x10 mm 80-PBGA Evaluation Board Preliminary Rev. 0.4 ROHS6 Temperature Pb-Free Range Yes – °C ...
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Package Outline Figure 5 illustrates the package details for the Si5374. Table 10 lists the values for the dimensions shown in the illustration. Figure 5. 80-Pin Plastic Ball Grid Array (PBGA) Symbol Min Nom A 1.22 1.39 A1 0.40 ...
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Si5374 9. Recommended PCB Layout Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design ...
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... Pin 1 Identifier “e1” Lead Free Finish Symbol (Pb-Free BGA Balls) Country of Origin Preliminary Rev. 0.4 Si5374 Si5374B-A-GL Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Manufacturing Code from the Assembly Purchase Order form. Circle = 0.75 mm Diameter Lower-Left Justified Circle = 1 ...
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Si5374 OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Added 1.8 V operation. Added 40 MHz reference oscillator Corrected Figure 5 title. Added comment to SFOUT register. Revision 0.2 to Revision 0.3 Updated ...
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N : OTES Preliminary Rev. 0.4 Si5374 63 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...