DS92LV1021AMSA National Semiconductor, DS92LV1021AMSA Datasheet - Page 11

• Manufacturer Part Number: DS92LV1021AMSA
• Manufacturer: National Semiconductor

Specifications of DS92LV1021AMSA

• Number Of Elements: 1
• Number Of Receivers: 10
• Number Of Drivers: 1
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Serializer
• Differential Output Voltage: 270mV
• Transmission Data Rate: 400Mbps
• Power Dissipation: 1.27W
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SSOP-EIAJ
• Lead Free Status / Rohs Status: Not Compliant

DIN
TCLK_R/F
DO+
DO−
DEN
PWRDN
TCLK
SYNC
DVCC
DGND
AVCC
AGND
SYNC PTRN
DATA (0–9)
DATA (0–9)
Serializer Pin Description
Truth Table
∼ Pulse 5-bits
* Inverted
** Device must be locked first
†
DIN (0–9)
Must be 1 before SYNC PTRN starts
DATA
DATA
RI
X
X
X
X
X
Pin Name
SYNC PTRN*
DATA (0–9)*
DATA (0–9)*
TCLK_R/F
RI−
X
X
X
X
X
1
0
SYSTEM CLK
I/O
O
O
I
I
I
I
I
I
I
I
I
I
RCLK_R/F
TCLK
L
K
X
X
X
X
X
1
0
18, 25, 20, 23
27, 28
15, 16
17, 26
3–12
1, 2
No.
13
22
21
19
24
14
SYNC1/SYNC2
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
REFCLK
1∼
X
X
X
X
0
0
Data Input. TTL levels inputs. Data on these pins are loaded into a
10-bit input register.
Transmit Clock Rising/Falling strobe select. TTL level input. Selects
TCLK active edge for strobing of DIN data. High selects rising
edge. Low selects falling edge.
+ Serial Data Output. Non-inverting Bus LVDS differential output.
− Serial Data Output. Inverting Bus LVDS differential output.
Serial Data Output Enable. TTL level input. A low, puts the Bus
LVDS outputs in TRI-STATE.
Powerdown. TTL level input. PWRDN driven low shuts down the
PLL and TRI-STATEs the outputs putting the device into a low
power sleep mode. This pin has an internal weak pull down.
Transmit Clock. TTL level input. Input for 16 MHz–40 MHz
(nominal) system clock.
Assertion of SYNC (high) for at least 1024 synchronization symbols
to be transmitted on the Bus LVDS serial output. Synchronization
symbols continue to be sent if SYNC continues asserted. TTL level
input. The two SYNC pins are ORed.
Digital Circuit power supply. DVCC voltage level should be identical
to the AVCC voltage level.
Digital Circuit ground. Ground potential should be the same as
AGND.
Analog power supply (PLL and Analog Circuits). AVCC voltage
level should be identical to the DVCC voltage level.
Analog ground (PLL and Analog Circuits). Ground potential should
be the same as DGND.
11
DEN
REN
0**
X
X
0
1
1
1
1
1
1
PWRDN
PWRDN
0
1
1
1
1
0
1
1
1
1
Description
SYNC PTRN
DATA (0–9)
DATA (0–9)
RCLK
DO+
CLK
L
K
Z
Z
Z
Z
SYNC PTRN*
DATA (0–9)*
DATA (0–9)*
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LOCK
DO−
1
Z
Z
Z
Z
0
0
†