LFEC3E-3TN144I Lattice, LFEC3E-3TN144I Datasheet - Page 11
LFEC3E-3TN144I
Manufacturer Part Number
LFEC3E-3TN144I
Description
IC FPGA 3.1KLUTS 97I/O 144-TQFP
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-3TN144I
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC3E-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
From Routing
From Routing
From Routing
From Routing
Routing
Routing
From
From
Routing
Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From
From
2-8
Routing
Routing
From
From
LatticeECP/EC Family Data Sheet
Routing
Routing
From
From
From Routing
From Routing
From Routing
From Routing
Architecture
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