LFEC3E-4TN144C Lattice, LFEC3E-4TN144C Datasheet - Page 63
LFEC3E-4TN144C
Manufacturer Part Number
LFEC3E-4TN144C
Description
IC FPGA 3.1KLUTS 97I/O 144-TQFP
Manufacturer
Lattice
Datasheet
1.LFEC3E-5TN144C.pdf
(163 pages)
Specifications of LFEC3E-4TN144C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 3-14. sysCONFIG Master Serial Port Timing
Figure 3-15. sysCONFIG Slave Serial Port Timing
Figure 3-16. Power-On-Reset (POR) Timing
CCLK (output)
CCLK (input)
V
1. Time taken from V
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
CC
/V
CFG[2:0]
DOUT
CCAUX
DOUT
DONE
CCLK
INITN
DIN
DIN
1
2
3
CC
or V
CCAUX
, whichever is the last to reach its V
t
t
t
SUSCDI
ICFG
SUMCDI
t
SUCFG
3-27
t
SSCL
t
VMC
Valid
MIN
.
t
HCFG
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
t
t
CODO
CODO
t
SSCH
t
t
HSCDI
HMCDI
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