LFXP3E-4TN100C Lattice, LFXP3E-4TN100C Datasheet - Page 307

• Manufacturer Part Number: LFXP3E-4TN100C
• Description: IC FPGA 3.1KLUTS 62I/O 100-TQFP
• Manufacturer: Lattice

Specifications of LFXP3E-4TN100C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
high), the Flow-Through instruction will be executed and the CSON pin will be driven low to enable the next
device’s chip select pin.
The DOUT/CSON bypass register will drive out a high upon power up and continue to do so until the execution of
the Bypass or Flow-Through instruction within the bitstream.
Chain Mode is not supported when configuring from internal Flash (SDM).
CSN and CS1N
Both CSN and CS1N are active low input pins with weak pull-ups and are used in parallel mode only. These inputs
are OR’ed and used to enable the D[0:7] data pins to receive or output a byte of data.
In non-SDM, when CSN or CS1N are high, the D[0:7], INITN, and BUSY pins are tri-stated. CSN and CS1N are
interchangeable when controlling the D[0:7], INITN, and BUSY pins.
When SDM is selected and CSN or CS1N are high, the D[0:7], INITN, and BUSY pins are tri-stated. If the Flash
has not been programmed a high on both CSN and CS1N will cause the LatticeXP to drive the INITN pin low to
reset the internal FPGA configuration circuitry. The LatticeXP will then monitor D[0:7] waiting for the configuration
preamble. CSN and CS1N are interchangeable when controlling the D[0:7], INITN, and BUSY pins.
During configuration or programming through the parallel sysCONFIG interface, CSN and SCIN should remain low
during the entire process. Deassertion of either of these signals will interrupt the process, requiring a new cycle to
properly transfer the data.
If SRAM or Flash will need to be accessed while the device is in user mode (the DONE pin is high) then the PER-
SISTENT preference must be set to ON in order to preserve these pins as CSN and CS1N.
WRITEN
The WRITEN pin is an active low input with a weak pull-up and used for parallel mode only. The WRITEN pin is
used to determine the direction of the data pins D[0:7]. The WRITEN pin must be driven low when a byte of data is
to be clocked into the device and driven high when data is to be read from the device.
If SRAM or Flash will need to be accessed while the part is in user mode (the DONE pin is high) then the PERSIS-
TENT preference must be set to ON in order to preserve this pin as WRITEN.
BUSY
In parallel mode the BUSY pin is a tri-stated output with a weak pull-up. The BUSY pin will be driven low by the Lat-
ticeXP device only when it is ready to receive a byte of data from the D[0:7] pins or a byte of data is ready for read-
ing. The BUSY pin can be used to support asynchronous peripheral mode (handshaking). This pin is used to
indicate that the LatticeXP needs extra time to execute a command.
If SRAM or Flash will need to be accessed while the part is in user mode (the DONE pin is high) then the PERSIS-
TENT preference must be set to ON in order to preserve this pin as BUSY.
D[0:7]
The D[0:7] pins support slave parallel mode only. The D[0:7] pins are tri-statable bi-directional I/O pins used for
data write and read. When the WRITEN signal is low, and the CSN and CS1N pins are low, the D[0:7] pins become
data inputs. When the WRITEN signal is driven high, and the CSN and CS1N pins are low, the D[0:7] pins become
data outputs. If either CSN or CS1N is high D[0:7] will be tri-state. D[0] is the most significant bit and D[7] is the
least significant bit.
If SRAM or Flash will need to be accessed while the part is in user mode (the DONE pin is high) then the PERSIS-
TENT preference must be set to ON in order to preserve these pins as D[0:7].
Care must be exercised during read back of EBR or PFU memory. It is up to the user to ensure that reading these
RAMs will not cause data corruption, i.e. these RAMs may not be read while being accessed by user code.
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