LFEC15E-3FN484C Lattice, LFEC15E-3FN484C Datasheet - Page 10
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LFEC15E-3FN484C
Manufacturer Part Number
LFEC15E-3FN484C
Description
IC FPGA 10.2KLUTS 288I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFECP15E-5FN256C.pdf
(163 pages)
Specifications of LFEC15E-3FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1231
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Lattice Semiconductor
Routing
There are many resources provided in the LatticeECP/EC devices to route signals individually or as busses with
related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing)
segments.
The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU).
The x1 and x2 connections provide fast and efficient connections in horizontal and vertical directions. The x2 and
x6 resources are buffered, the routing of both short and long connections between PFUs.
The ispLEVER design tool suite takes the output of the synthesis tool and places and routes the design. Generally,
the place and route tool is completely automatic, although an interactive routing editor is available to optimize the
design.
Clock Distribution Network
The clock inputs are selected from external I/O, the sysCLOCK™ PLLs or routing. These clock inputs are fed
through the chip via a clock distribution system.
Primary Clock Sources
LatticeECP/EC devices derive clocks from three primary sources: PLL outputs, dedicated clock inputs and routing.
LatticeECP/EC devices have two to four sysCLOCK PLLs, located on the left and right sides of the device. There
are four dedicated clock inputs, one on each side of the device. Figure 2-6 shows the 20 primary clock sources.
Figure 2-6. Primary Clock Sources
Clock Input
PLL Input
PLL Input
Note: Smaller devices have two PLLs.
PLL
PLL
From Routing
From Routing
To Quadrant Clock Selection
20 Primary Clock Sources
Clock Input
Clock Input
2-7
From Routing
From Routing
LatticeECP/EC Family Data Sheet
PLL
PLL
PLL Input
Clock Input
PLL Input
Architecture
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