LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet

LFE2-20E-5FN256I

Manufacturer Part Number

LFE2-20E-5FN256I

Description

IC FPGA 21KLUTS 193I/O 256FPBGA

Manufacturer

Lattice

Series

ECP2r

Datasheets

1.LFE2-12SE-6FN256C.pdf (389 pages)

2.LFE3-35EA-8FN672I.pdf (21 pages)

3.LFE2-20E-5FN256I.pdf (4 pages)

4.LFE2-20E-5FN256I.pdf (769 pages)

Specifications of LFE2-20E-5FN256I

Number Of Logic Elements/cells

21000

Number Of Labs/clbs

2625

Total Ram Bits

282624

Number Of I /o

193

Number Of Gates

Voltage - Supply

1.14 V ~ 1.26 V

Mounting Type

Surface Mount

Operating Temperature

-40°C ~ 100°C

Package / Case

256-BGA

Lead Free Status / Rohs Status

Lead free / RoHS Compliant

Other names

220-1170
LFE2-20E-5FN256I
Q6411457

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

LFE2-20E-5FN256I

Quantity:

1 831

Company:

BOSTOCK HK LIMITED

Part Number:

LFE2-20E-5FN256I

Manufacturer:

Lattice Semiconductor Corporation

Quantity:

10 000

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LatticeECP2/M Family

Exceptional Performance – Uncommon Value

l o W - c o s t

The LatticeECP2™ (EConomy Plus 2nd generation)

and LatticeECP2M™ families, collectively referred to as

LatticeECP2/M, redefine the low-cost FPGA category. By

integrating features and capabilities previously available only

on higher cost / high performance FPGAs, these families

dramatically expand the range of applications that can take

advantage of low-cost FPGA products.

Features that the LatticeECP2 family brings to the low cost

FPGA category include high performance DSP blocks, up to

70K LUT capacity, support for DDR2 memory interfaces at

533Mbps and up to 840Mbps generic LVDS performance.

The LatticeECP2 also provides enhanced FPGA configuration

options with features such as dual boot, bitstream encryption

and TransFR™ I/O capability.

The LatticeECP2M includes embedded SERDES, increases

density to 95K LUTs at under 0.35W static power, and pro-

vides significantly higher memory capacity, up to 5.3Mbits.

The SERDES supports many common serial packet protocols

including PCI Express and Ethernet (1GbE & SGMII).

The LatticeECP2/M devices are an excellent choice for a wide

variety of applications, including, low-cost networking, blade

servers, network access equipment, consumer electronics,

industrial, medical, software defined radio, wireless commu-

nications, military and automotive.

FPGA Fabric Features and Capabilities



Low Cost FPGAs

• Features optimized for mainstream applications

• Balanced logic-memory-I/O resources

Lowest Power SERDES-based FPGA

• 95K LUTs with under 0.35W static power

Extensive Density and Package Options

• 6K to 95K LUT4s, 90 to 583 I/O

• Density migration supported

• TQFP, PQFP and fpBGA packaging options

• Pb-free / RoHS-compliant options

Embedded and Distributed Memory

• 12K to 202K bits distributed memory

• 55K to 5.3M bits sysMEM™ block memory

Flexible sysIO™ Buffers

• LVCMOS 33/25/18/15/12

• PCI

• SSTL3/2/18 & HSTL15 & HSTL18

• LVDS, RSDS, Bus-LVDS, MLVDS & LVPECL

sysCLOCK™ PLL and DLL

• 2 DLLs per device

• 2 to 8 PLLs per device

System Level Support

• IEEE 1149.1 boundary scan

• 1.2-volt power supply

f p g a s

m o r e

W i t h

h i g h - p e r f o r m a n c e

o f

LatticeECP2 Features and Benefits

t h e

EMBEddEd SErdES



LOW POWEr



sysdSP™ BLOCkS



HigH-SPEEd i/O



SuPEriOr COnFiguratiOn OPtiOnS



3.125Gbps with Low 100mW Power per Channel

Receive Equalization and Transmit Pre-emphasis

Supports PCI Express, Ethernet (1GbE & SGMI)

95K LUTs with under 0.35W Static Power

Improve Thermal Management, System Reliability

Multiply, Accumulate, Addition & Subtraction in

Implement High-Performance DSP Functions

Up to 168 18x18 Multipliers Give 63 GMAC DSP

I/O Cells Include Dedicated DDR Mux/Demux,

Pre-Engineered Source Synchronous Interfaces

• DDR1 400Mbps; DDR2 533Mbps

• SPI4.2 750Mbps

• Generic 840Mbps

Industry Standard SPI Boot Flash Interface

Bitstream Encryption Prevents Design Piracy

Dual Boot Provides Backup Configuration Copy

TransFR I/O Supports Updates While System

Plus Multiple Other Standards

and Reduce Overall System Cost

Dedicated Blocks

Such as FIR, FFT and NCO in a Low-Cost FPGA

Performance

DQS Alignment and Gearbox Logic

Operates

b e s t

f e a t u r e s

Related parts for LFE2-20E-5FN256I

LFE2-20E-5FN256I Summary of contents

Page 1

... The SERDES supports many common serial packet protocols including PCI Express and Ethernet (1GbE & SGMII). The LatticeECP2/M devices are an excellent choice for a wide variety of applications, including, low-cost networking, blade servers, network access equipment, consumer electronics, industrial, medical, software defined radio, wireless commu- nications, military and automotive ...

Page 2

... TransFR field updates. The ECP2M devices provide all the features of the LatticeECP2 family and adds a high performance SERDES block capable of support- ing many common packet based protocols including PCI Express, Ethernet (1GbE and SGMII) and related packet protocol standards ...

Page 3

... LUTs *Based on power calculator results Pre-Engineered Source Synchronous I/O The I/O cells in the LatticeECP2/M de- vices contain a number of pre-engineered elements to allow the easy implementa- tion of source synchronous interfaces such as those found on DDR1/2 memo- ries, SPI4.2 systems and high-speed ADC/DACs. ...

Page 4

... LatticeECP2, LatticeECP2M, sysCLOCK, sysCONFIG, sysDSP, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...

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