LFE3-35EA-8FN484C Lattice, LFE3-35EA-8FN484C Datasheet - Page 104
LFE3-35EA-8FN484C
Manufacturer Part Number
LFE3-35EA-8FN484C
Description
IC FPGA 33KLUTS 295I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-35EA-8FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
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Lattice Semiconductor
HDMI (High-Definition Multimedia Interface) Electrical and Timing
Characteristics
AC and DC Characteristics
Table 3-22. Transmit and Receive
Transmit
Intra-pair Skew
Inter-pair Skew
TMDS Differential Clock Jitter
Receive
R
V
TMDS Clock Jitter
1. Output buffers must drive a translation device. Max. speed is 2Gbps. If translation device does not modify rise/fall time, the maximum speed
2. Input buffers must be AC coupled in order to support the 3.3V common mode. Generally, HDMI inputs are terminated by an external cable
T
ICM
is 1.5Gbps.
equalizer before data/clock is forwarded to the LatticeECP3 device.
Symbol
Termination Resistance
Input AC Common Mode Voltage (50-ohm Setting)
Clock Jitter Tolerance
1, 2
Description
3-51
DC and Switching Characteristics
LatticeECP3 Family Data Sheet
Min. Spec.
Spec. Compliance
40
—
—
—
—
—
Max. Spec.
0.25
0.25
800
75
60
50
Ohms
Units
mV
ps
ps
UI
UI