LFXP2-40E-7FN484C Lattice, LFXP2-40E-7FN484C Datasheet - Page 16
LFXP2-40E-7FN484C
Manufacturer Part Number
LFXP2-40E-7FN484C
Description
IC FPGA 40KLUTS 363I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP2-40E-5FN484I.pdf
(92 pages)
Specifications of LFXP2-40E-7FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-40E-7FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LatticeXP2-30 and smaller devices have six secondary clock regions. All devices in the LatticeXP2 family have four
secondary clocks (SC0 to SC3) which are distributed to every region.
The secondary clock muxes are located in the center of the device. Figure 2-12 shows the mux structure of the
secondary clock routing. Secondary clocks SC0 to SC3 are used for clock and control and SC4 to SC7 are used for
high fan-out signals.
Figure 2-11. Secondary Clock Regions XP2-40
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
I/O Bank 0
I/O Bank 5
Region 1
Region 2
Region 3
Region 4
2-13
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region 5
I/O Bank 1
Region 6
Region 7
Region 8
I/O Bank 4
LatticeXP2 Family Data Sheet
Vertical Routing
Channel Regional
Boundary
EBR Row
Regional
Boundary
EBR Row
Regional
Boundary
DSP Row
Regional
Boundary
Architecture
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