LFE3-150EA-6FN1156C Lattice, LFE3-150EA-6FN1156C Datasheet - Page 31
LFE3-150EA-6FN1156C
Manufacturer Part Number
LFE3-150EA-6FN1156C
Description
IC FPGA 149KLUTS 586I/O 1156-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-6FN1156C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
MULTADDSUBSUM DSP Element
In this case, the operands AA and AB are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands BA and BB of Slice 0. Additionally, the operands AA and AB are multiplied and the
result is added/subtracted with the result of the multiplier operation of operands BA and BB of Slice 1. The results
of both addition/subtractions are added by the second ALU following the slice cascade path. The user can enable
the input, output and pipeline registers. Figure 2-30 and Figure 2-31 show the MULTADDSUBSUM sysDSP ele-
ment.
Figure 2-30. MULTADDSUBSUM Slice 0
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
I
C
IR
AA
MULTA
OR
PR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-28
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
OR
PR
LatticeECP3 Family Data Sheet
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture
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