SL72P4M128M8M-B05AYU STEC, SL72P4M128M8M-B05AYU Datasheet - Page 10

• Manufacturer Part Number: SL72P4M128M8M-B05AYU
• Manufacturer: STEC

Specifications of SL72P4M128M8M-B05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 9Gb
• Access Time (max): 600ps
• Maximum Clock Rate: 200MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 4.77A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P4M128M8M-B05AY(W)U
DDR2 IDD Specifications and Conditions
Notes: 1–5. Values shown for DDR2 SDRAM components only.
Symbol—Parameter/Condition
Max DDR2 IDD Values
IDD0—Operating one bank active-precharge current; tCK =
tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING.
IDD1—Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC
= tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is
HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W.
IDD2P—Precharge power-down current; All device banks idle;
tCK = tCK (IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
IDD2Q—Precharge quiet standby current; All device banks idle;
tCK = tCK (IDD); CKE is HIGH, /CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
IDD2N—Precharge standby current; All device banks idle; tCK =
tCK (IDD); CKE is HIGH, /CS is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD3P—Active power-down current; All device banks open; tCK
= tCK (IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING.
IDD3N—Active standby current; All device banks open; tCK =
tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is
HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Symbol
IDD0
IDD1
IDD2P
IDD2Q
IDD2N
IDD3P
Fast PDN Exit MR[12] = 0
IDD3P
Slow PDN Exit MR[12] = 1
IDD3N
IDD4W
IDD4R
IDD5
IDD6
IDD7
DDR2-400
1,710
1,800
1,170
2,340
2,520
3,330
4,770
Document Part Number 61000-02973-106 July 2007 Page 10
144
450
540
540
270
99
IDD4W—Operating burst write current; All device banks open,
Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, /
CS is HIGH between valid commands; Address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD4R—Operating burst read current; All device banks open,
Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD5—Burst refresh current; tCK = tCK (IDD); Refresh command
at every tRFC (IDD) interval; CKE is HIGH, /CS is HIGH between
valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD6—Self refresh current; CK and /CK at 0V; CKE ≤ 0.2V; Other
control and address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD7—Operating bank interleave read current; All device banks
interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD
(IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD =
tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, /CS is HIGH
between valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See IDD7
Conditions for detail.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
240-PIN RDIMM