TXC-06412BROG Transwitch Corporation, TXC-06412BROG Datasheet - Page 185

• Manufacturer Part Number: TXC-06412BROG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BROG

• Lead Free Status / Rohs Status: Compliant

1 8 5 o f 2 26
Offset
0x0000
0x0100
0x0200
0x0400
12.10 TOH GENERATOR
Bits
Common_Config
Line_Config
TTI_Contents
TOH_Contents
Name
Table 34: TOH Generator
See desc.
- Memory Maps and Bit Descriptions -
Init
All 0x0 rw
rw
rw
rw
Access
T_TOHG_Common_Config
General configuration.
Array (4) of T_TOHG_Line_Config
Offset between two elements = 0x8.
Array index indicates the line (= line number - 1).
Configuration.
Array (64) of byte
Offset between two elements = 0x2.
Array index indicates the TTI byte number.
This array contains the TTI sequence for the four lines:
Note: Bytes 16 to 63 are not used in STM-4 mode.
Array (324) of nine_bits
Offset between two elements = 0x2.
Array index indicates the TOH byte number.
This array contains the TOH for a single STM-4 or 4 times STM-1. Each
TOH byte is represented by a nine bit word. The most significant bit
determines the source of the corresponding byte (0x0 = internal memory,
0x1 = TOH Port Interface). This way of determining the source of a byte is
the default behavior. For certain bytes (DCC-bytes, M1, K1, K2), other
sources than internal memory or TOH-Port can be selected by extra
settings which override this default behavior.
The least significant byte contains the byte value when this bytes has to be
inserted from memory.
The order in which bytes are mapped in memory is the same order as
these bytes appear in the TOH. For STM-1 mode the columns are byte
interleaved: column #1 corresponds to line 1, column 2 to line 2, etc.
The byte number can easily be calculated as follows:
byte number = (a-1)x36 + (b-1)x4 + c-1
where
See also [ITU-T G.707/Y.1322] for the TOH bytes locations.
Note 1: Space is also reserved for the administrative Unit Pointer bytes (a
= 4) but these bytes are not used.
Note 2: K1/K2 can not be sourced from this internal memory. Separate
sixteen bit registers are provided for these bytes to guarantee that K1 and
K2 are kept together.
Note 3: B1 and B2 byte locations serve as an error mask which will be
EXORed with the calculated BIP. These locations must be 0x00 for normal
operation.
Note 4: A1 bytes (bytes 0-11) are initialized to 0xF6, A2 bytes (bytes 12-
23) are initialized to 0x28. All other entries are initialized to 0x00.
• bytes 0-15: TTI message for line 1
• bytes 16-31: TTI message for line 2
• bytes 32-47: TTI message for line 3
• bytes 48-63: TTI message for line 4
• a = row number (1 to 3, 5 to 9),
• b = multi-column number (1 to 9),
• c, for STM-4 mode = depth of the interleave within the multi-column
• c, for STM-1 mode = line number (1-4).
(1-4),
(T_TOH_GENERATOR)
(See page
Description
PRELIMINARY TXC-06412B-MB, Ed. 2
(See page
186.)
PHAST-12P Device
186.)
DATA SHEET
TXC-06412B
June 2005