DP83848IVVX/HALF National Semiconductor, DP83848IVVX/HALF Datasheet - Page 35

• Manufacturer Part Number: DP83848IVVX/HALF
• Manufacturer: National Semiconductor

Specifications of DP83848IVVX/HALF

• Lead Free Status / Rohs Status: Compliant

5.4 Power Feedback Circuit
To ensure correct operation for the DP83848I, parallel caps
with values of 10
placed close to pin 23 (PFBOUT) of the device.
Pin 18 (PFBIN1) and pin 37 (PFBIN2) must be connected
to pin 23 (PFBOUT), each pin requires a small capacitor
(.1 F). See Figure 13 below for proper connections.
1
This limit is provided as a guideline for component selection and to guaranteed by production testing.
Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock Jitter Tolerance,“ for details on jitter performance.
Pin 23 (PFBOUT)
Pin 37 (PFBIN2)
Pin 18 (PFBIN1)
Rise / Fall Time
Load Capacitance
Parameter
Frequency
Frequency
Frequency
Symmetry
Tolerance
Stability
Parameter
Frequency
Frequency
Frequency
Jitter
Jitter
Tolerance
Figure 13. Power Feeback Connection
Stability
.1 F
F (Tantalum) and 0.1
.1 F
40%
Min
Min
25
10 F
Table 8. 50 MHz Oscillator Specification
Table 9. 25 MHz Crystal Specification
+
-
Typ
50
F should be
Typ
.1 F
25
35
5.5 Power Down/Interrupt
The Power Down and Interrupt functions are multiplexed
on pin 7 of the device. By default, this pin functions as a
power down input and the interrupt function is disabled.
Setting bit 0 (INT_OE) of MICR (0x11h) will configure the
pin as an active low interrupt output.
5.5.1 Power Down Control Mode
The PWR_DOWN/INT pin can be asserted low to put the
device in a Power Down mode. This is equivalent to setting
bit 11 (Power Down) in the Basic Mode Control Register,
BMCR (0x00h). An external control signal can be used to
drive the pin low, overcoming the weak internal pull-up
resistor. Alternatively, the device can be configured to ini-
tialize into a Power Down state by use of an external pull-
down resistor on the PWR_DOWN/INT pin. Since the
device will still respond to management register accesses,
setting the INT_OE bit in the MICR register will disable the
PWR_DOWN/INT input, allowing the device to exit the
Power Down state.
5.5.2 Interrupt Mechanisms
The interrupt function is controlled via register access. All
interrupt sources are disabled by default. Setting bit 1
(INTEN) of MICR (0x11h) will enable interrupts to be out-
put, dependent on the interrupt mask set in the lower byte
of the MISR (0x12h). The PWR_DOWN/INT pin is asyn-
chronously asserted low when an interrupt condition
occurs. The source of the interrupt can be determined by
reading the upper byte of the MISR. One or more bits in the
800
800
60%
Max
+50
+50
6
1
1
Max
+50
+50
40
Units
MHz
nsec
psec
psec
ppm
ppm
Units
MHz
ppm
ppm
pF
Operational Temperature
Operational Temperature
20% - 80%
Duty Cycle
Condition
Short term
Long term
Temperature
1 year aging
www.national.com
Operational
Condition