AM28F010-90JI Spansion Inc., AM28F010-90JI Datasheet - Page 6

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AM28F010-90JI

Manufacturer Part Number
AM28F010-90JI
Description
Manufacturer
Spansion Inc.
Datasheet

Specifications of AM28F010-90JI

Cell Type
NOR
Density
1Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
17b
Operating Supply Voltage (typ)
5V
Operating Temp Range
-40C to 85C
Package Type
PLCC
Program/erase Volt (typ)
11.4 to 12.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8b
Number Of Words
128K
Supply Current
30mA
Mounting
Surface Mount
Pin Count
32
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM28F010-90JI
Manufacturer:
LAI
Quantity:
5 555
PIN DESCRIPTION
A0–A16
A
hold addresses during write cycles.
CE
Chip Enable active low input activates the chip’s con-
trol logic and input buffers. Chip Enable high will dese-
lect the device and operates the chip in stand-by mode.
DQ0–DQ7
Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
NC
No Connect-corresponding pin is not connected
internally to the die.
OE
Output Enable active low input gates the outputs of the
device through the data buffers during memory read
cycles. Output Enable is high during command
sequencing and program/erase operations.
6
ddress Inputs for memory locations. Internal latches
#
#
(E
(G
#
#
)
)
Am28F010
V
Power supply for device operation. (5.0 V
V
Program voltage input. V
order to write to the command register. The command
register controls all functions required to alter the mem-
ory array contents. Memory contents cannot be altered
when V
V
Ground
WE
Write Enable active low input controls the write function
of the command register to the memory array. The tar-
get address is latched on the falling edge of the Write
Enable pulse and the appropriate data is latched on the
rising edge of the pulse. Write Enable high inhibits
writing to the device.
CC
PP
SS
#
(W
PP
#
)
V
CC
+2 V.
PP
must be at high voltage in
5% or 10%)

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