CY7C144-35AC Cypress Semiconductor Corp, CY7C144-35AC Datasheet - Page 9

• Manufacturer Part Number: CY7C144-35AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C144-35AC

• Density: 64Kb
• Access Time (max): 35ns
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 160mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Word Size: 8b
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-06034 Rev. *C
Switching Waveforms
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)
DATA OUT
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
Notes:
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either signal
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during write.
ADDRESS
SEM OR CE
SEM OR CE
DATA OUT
DATA IN
ADDRESS
can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
be placed on the bus for the required t
pulse can be as short as the specified t
DATA IN
R/W
OE
R/W
t
SA
(continued)
t
SD
SA
PWE
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write
t
.
HZOE
t
SCE
t
SCE
t
AW
t
HIGH IMPEDANCE
AW
t
HZWE
t
WC
[21, 22, 23]
t
WC
[21, 23, 24]
t
PWE
t
PWE
t
SD
PWE
DATA VALID
t
SD
HIGH IMPEDANCE
DATAVALID
or (t
HZWE
+ t
SD
t
) to allow the I/O drivers to turn off and data to
HD
t
t
HD
LZWE
t
HA
t
LZOE
t
HA
CY7C144
CY7C145
Page 9 of 20
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