MC74HC595AN ON Semiconductor, MC74HC595AN Datasheet - Page 6

• Manufacturer Part Number: MC74HC595AN
• Manufacturer: ON Semiconductor
• Type: Not Requiredr

Specifications of MC74HC595AN

• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logic Family: HC
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Output Type: 3-State
• Package Type: PDIP
• Propagation Delay Time: 225ns
• Operating Temp Range: -55C to 125C
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 6V
• Operating Temperature Classification: Military
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / Rohs Status: Not Compliant

SR = shift register contents
LR = latch register contents
INPUTS
A (Pin 14)
8−bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
this input causes the data at the Serial Input pin to be shifted
into the 8−bit shift register.
Reset (Pin 10)
low on this pin resets the shift register portion of this device
only. The 8−bit latch is not affected.
Latch Clock (Pin 12)
this input latches the shift register data.
Reset shift register
Shift data into shift
register
Shift register remains
unchanged
Transfer shift register
contents to latch
register
Latch register remains
unchanged
Enable parallel outputs
Force outputs into high
impedance state
Serial Data Input. The data on this pin is shifted into the
Shift Register Clock Input. A low− to−high transition on
Active−low, Asynchronous, Shift Register Reset Input. A
Storage Latch Clock Input. A low−to−high transition on
Operation
Reset
H
H
H
X
X
X
L
D = data (L, H) logic level
U = remains unchanged
Serial
Input
A
X
D
X
X
X
X
X
L, H, ↓
L, H, ↓
Clock
Inputs
Shift
X
↑
X
X
X
PIN DESCRIPTIONS
L, H, ↓
L, H, ↓
L, H, ↓
L, H, ↓
http://onsemi.com
FUNCTION TABLE
Clock
Latch
X
X
↑
↑ = Low−to−High
↓ = High−to−Low
Output
Enable
6
H
L
L
L
L
L
L
Output Enable (Pin 13)
data from the latches to be presented at the outputs. A high
on this input forces the outputs (Q
high−impedance state. The serial output is not affected by
this control unit.
OUTPUTS
Q
SQ
eighth stage of the 8−bit shift register. This output does not
have three−state capability.
A
Active−low Output Enable. A low on this input allows the
Noninverted, 3−state, latch outputs.
Noninverted, Serial Data Output. This is the output of the
H
− Q
SR
(Pin 9)
Contents
D → SR
H
Register
N
(Pins 15, 1, 2, 3, 4, 5, 6, 7)
Shift
→ SR
U
U
L
*
*
*
A
N+1
;
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
SR
Resulting Function
Contents
Register
Latch
N
→ LR
U
U
U
U
**
**
N
SR
Output
Serial
G
SQ
→ SR
U
U
L
*
*
*
H
A
−Q
H
H
) into the
Outputs
Q
Parallel
Enabled
A
SR
U
U
U
U
Z
− Q
N
H