UPD431000AGW-70LL Renesas Electronics America, UPD431000AGW-70LL Datasheet - Page 21

• Manufacturer Part Number: UPD431000AGW-70LL
• Manufacturer: Renesas Electronics America

Specifications of UPD431000AGW-70LL

• Density: 1Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 70mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Data Retention Timing Chart
(1) /CE1 Controlled
Note A version : 3.0 V, B version : 2.7 V
Remark
(2) CE2 Controlled
Note A version : 3.0 V, B version : 2.7 V
Remark
V
V
CCDR
On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ V
≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
CCDR
V
V
V
V
IL
4.5 V
IH
IL
4.5 V
IH
(MAX.)
(MAX.)
(MIN.)
(MIN.)
(MIN.)
(MIN.)
GND
GND
V
Note
V
Note
CC
CC
t
CDR
t
CDR
CE2
/CE1
Data Sheet M11657EJEV0DS
Data retention mode
Data retention mode
/CE1 ≥ V
CE2 ≤ 0.2 V
CC
– 0.2 V
t
t
R
R
μ
CC
PD431000A
− 0.2 V or CE2
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