M30624FGMFP Renesas Electronics America, M30624FGMFP Datasheet - Page 18

• Manufacturer Part Number: M30624FGMFP
• Manufacturer: Renesas Electronics America

Specifications of M30624FGMFP

• Cpu Family: M16C
• Device Core Size: 16/32Bit
• Frequency (max): 10MHz
• Interface Type: UART
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 20KB
• # I/os (max): 87
• Number Of Timers - General Purpose: 11
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 10-chx10-bit
• On-chip Dac: 2-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Timing
Switching characteristics (referenced to V
85
Table 1.26.23. Memory expansion and microprocessor modes
Note 1: Calculated according to the BCLK frequency as follows:
Note 2: Specify a product of –40°C to 85°C to use it.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d(BCLK-AD)
h(BCLK-AD)
h(RD-AD)
h(WR-AD)
d(BCLK-CS)
h(BCLK-CS)
h(RD-CS)
h(WR-CS)
d(BCLK-RD)
h(BCLK-RD)
d(BCLK-WR)
h(BCLK-WR)
d(BCLK-DB)
h(BCLK-DB)
d(DB-WR)
h(WR-DB)
d(BCLK-ALE)
h(BCLK-ALE)
d(AD-ALE)
h(ALE-AD)
d(AD-RD)
d(AD-WR)
dZ(RD-AD)
Symbol
o
C (Note 2), CM15 = “1” unless otherwise specified)
td(AD – ALE) =
th(RD – AD) =
th(WR – AD) =
th(RD – CS) =
th(WR – CS) =
td(DB – WR) =
th(WR – DB) =
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (WR standard)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
RD signal output hold time
WR signal output delay time
Data output delay time (WR standard)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
ALE signal output hold time(Address standard)
Post-address WR signal output delay time
Address output floating start time
Chip select output hold time (BCLK standard)
Data output hold time (BCLK standard)
Post-address RD signal output delay time
(when accessing external memory area with wait, and select multiplexed bus)
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
f(BCLK) X 2
10
Parameter
10
10
10
10
10
10
9
9
9
9
9
9
X 3
9
– 80
– 45
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
[ns]
CC
= 3V, V
Measuring condition
Figure 1.26.1
SS
= 0V at Topr = – 20
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Min.
– 4
40
4
Standard
4
4
0
0
0
0
o
Max.
C to 85
60
60
60
60
80
60
8
(Low voltage version)
Mitsubishi microcomputers
o
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C / – 40
M16C / 62M Group
o
C to
17