M5M51008DFP-70HI Renesas Electronics America, M5M51008DFP-70HI Datasheet
M5M51008DFP-70HI
Specifications of M5M51008DFP-70HI
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M5M51008DFP-70HI Summary of contents
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... The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp ...
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... DESCRIPTION The M5M51008DFP,VP,RV,KV are a 1048576-bit CMOS static RAM organized as 131072 word by 8-bit which are fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor (TFT) load cells and CMOS periphery result in a high density and low power static RAM ...
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... A10 Pin numbers inside dotted line show those of TSOP M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM When setting and OE. a non-selectable mode in which both reading and writing are 1 2 disabled. In this mode, the output stage high- impedance state, allowing OR-tie with other chips and memory expansion by ...
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... Input capacitance C I Output capacitance C O Note 3: Direction for current flowing into positive (no mark). 4: Typical value is Vcc = 5V 25°C M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM Conditions With respect to GND Ta=25°C (Ta= –40~85°C, Vcc=5V±10%, unless otherwise noted) Test conditions ...
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... Output disable time from W low t dis(OE) Output disable time from OE high t en(W) Output enable time from W high t en(OE) Output enable time from OE low M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM (Ta= –40~85°C, 5V±10% unless otherwise noted ) (-55HI) (for dis , dis Ver ...
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... TIMING DIAGRAMS Read cycle A 0~ (Note (Note 5) OE (Note "H" level Write cycle (W control mode (Note (Note 1~8 M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM a( (S1 (S2 (OE (OE (S1 (S2) DATA VALID (S1 (S2 (A-WH ( (W) rec (W) t dis ( (W) t dis (OE) DATA IN STABLE ...
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... DQ 1~8 Note 5: Hatching indicates the state is "don't care". 6: Writing is executed while S 7: When the falling edge simultaneously or prior to the falling edge rising edge Don't apply inverted phase signal externally when DQ pin is output mode. M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM (A) ...
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... Note 9: On the power down mode by controlling S S 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state control mode 0.2V M5M51008DFP,VP,RV,KV -55HI, -70HI 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM (Ta= –40~85°C, unless otherwise noted) Test conditions 2.2V Vcc(PD) 2V Vcc(PD) 2.2V 4.5V Vcc(PD) Vcc(PD)<4. ...
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Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to ...