AT49F1025-35JC Atmel, AT49F1025-35JC Datasheet - Page 2

• Manufacturer Part Number: AT49F1025-35JC
• Manufacturer: Atmel

Specifications of AT49F1025-35JC

• Cell Type: NOR
• Density: 1Mb
• Access Time (max): 35ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 16b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: PLCC
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 16b
• Number Of Words: 64K
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

Block Diagram
Device Operation
2
AT49F1024/1025
read and programming operation of the device. Reading data out of the device is similar
to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by
erasing a block of data (entire chip or main memory block) and then programming on a
word-by-word basis. The typical word programming time is a fast 10 µs. The end of a
program cycle can be optionally detected by the Data Polling feature. Once the end of a
byte program cycle has been detected, a new access for a read or program can begin.
The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 8K word boot block section includes a reprogramming write lockout feature
to provide data integrity. The boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is permanently protected from being erased
or reprogrammed.
READ: The AT49F1024/1025 is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high impedance state whenever
CE or OE is high. This dual line control gives designers flexibility in preventing bus
contention.
CHIP ERASE: When the boot block programming lockout feature is not enabled, the
boot block and the main memory block will erase together from the same Chip Erase
command (See Command Definitions table). If the boot block lockout function has been
enabled, data in the boot section will not be erased. However, data in the main memory
section will be erased. After a chip erase, the device will return to the read mode.
MAIN MEMORY ERASE: As an alternative to the chip erase, a main memory block
erase can be performed, which will erase all words not located in the boot block region
to an FFFFH. Data located in the boot region will not be changed during a main memory
block erase. The Main Memory Erase command is a six-bus cycle operation. The
address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input
is latched on the rising edge of WE. The main memory erase starts after the rising edge
of WE of the sixth cycle. Please see main memory erase cycle waveforms. The main
memory erase operation is internally controlled; it will automatically time to completion.
WORD PROGRAMMING: Once the memory array is erased, the device is programmed
(to a logic “0”) on a word-by-word basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming
is accomplished via the internal device command register and is a four-bus cycle
ADDRESS
INPUTS
GND
VCC
WE
OE
CE
OE, CE, AND WE
Y DECODER
X DECODER
LOGIC
DATA INPUTS/OUTPUTS
BLOCK (8K WORDS)
OPTIONAL BOOT
INPUT/OUTPUT
MAIN MEMORY
(56K WORDS)
DATA LATCH
I/O15 - I/O0
Y-GATING
BUFFERS
16
FFFFH
2000H
1FFFH
0000H
0765I–05/01