AT45DB161-TC Atmel, AT45DB161-TC Datasheet
AT45DB161-TC
Specifications of AT45DB161-TC
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AT45DB161-TC Summary of contents
Page 1
... The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of 528 bytes each. In addition to the main memory, the AT45DB161 also con- tains two SRAM data buffers of 528 bytes each. The buffers allow receiving of data ...
Page 2
... AT45DB161 does not require high-input voltages for pro- gramming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read opera- tions. The AT45DB161 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don’t care bits. In the AT45DB161, the first two address bits are reserved for larger density devices (see Notes on page 10), the next 12 address bits ...
Page 4
... When a low-to-high transition AT45DB161 4 occurs on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory ...
Page 5
Block Erase Addressing PA11 PA10 PA9 PA8 • • • • • • • • • • • • ...
Page 6
... The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB161, the three bits are 1, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a ...
Page 7
... This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT45DB161 0°C to 70°C -40°C to 85°C 2.7V to 3.6V 7 ...
Page 8
... PE t Block Erase Time BE t RESET Pulse Width RST t RESET Recovery Time REC Input Test Waveforms and Measurement Levels 2.4V AC DRIVING LEVELS 0.45V < (10 AT45DB161 8 Condition CS, RESET all inputs at IH CMOS levels MHz mA 3.6V OUT 3. CMOS levels CMOS levels I 1.6 mA ...
Page 9
AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a high- to-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both ...
Page 10
... It is recommended that “r” logical “0” for densities of 16M bits or smaller. 3. For densities larger than 16M bits, the “r” bits become the most significant Page Address bit for the appropriate density. AT45DB161 10 tRST ...
Page 11
... Main Memory Page Program through Buffers PA11-6 CMD Buffer Write CS SI CMD Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page Each transition represents 8 bits and 8 clock cycles FLASH MEMORY ARRAY MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 MAIN MEMORY PAGE ...
Page 12
... SO Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer Buffer Read Each transition represents 8 bits and 8 clock cycles AT45DB161 12 FLASH MEMORY ARRAY MAIN MEMORY PAGE READ I/O INTERFACE SO PA5-0, BA9-8 BA7-0 X Starts reading page data into buffer CMD ...
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Detailed Bit-level Read Timing – Inactive Clock Polarity Low Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read ...
Page 14
... Detailed Bit-level Read Timing – Inactive Clock Polarity High Main Memory Page Read CS SCK 1 2 tSU COMMAND OPCODE Buffer Read CS SCK 1 2 tSU COMMAND OPCODE Status Register Read CS SCK tSU HIGH-IMPEDANCE SO AT45DB161 HIGH-IMPEDANCE HIGH-IMPEDANCE COMMAND OPCODE DATA OUT MSB DATA OUT ...
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Table 1. Main Memory Buffer 1 Buffer 2 Page Read Read Read 52H 54H 56H ...
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... PA5 PA5 PA5 PA4 PA4 PA4 PA3 PA3 PA3 PA2 PA2 PA2 PA1 PA1 PA1 PA0 PA0 PA0 AT45DB161 16 Buffer 2 to Main Memory Page Program without Page Block Built-in Erase Erase Erase Opcode 89H 81H 50H PA11 PA11 PA11 PA10 PA10 ...
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Figure 1. Algorithm for Sequentially Programming or Reprogramming an Entire Sector MAIN MEMORY PAGE PROGRAM Notes: 1. This type of algorithm is used for applications in which an entire sector is programmed sequentially, filling the sector page- by-page ...
Page 18
... PA10 • • • • • • AT45DB161 18 START provide address of page to modify MAIN MEMORY PAGE to BUFFER TRANSFER (53H, 55H) BUFFER WRITE (84H, 87H) (82H, 85H) BUFFER to MAIN MEMORY PAGE PROGRAM (83H, 86H) (2) Auto Page Rewrite (58H, 59H) INCREMENT PAGE (2) ADDRESS POINTER ...
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... Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) 24C2 24-ball Array Plastic Chip-Scale Ball Grid Array (CBGA) Ordering Code AT45DB161-JC AT45DB161-RC AT45DB161-TC AT45DB161-CC AT45DB161-JI AT45DB161-RI AT45DB161-TI AT45DB161-CI Package Type Package Operation Range ...
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... E 1.00 (0,039) BSC NON-ACCUMULATIVE *Controlling dimension: millimeters 28R, 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) AT45DB161 20 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE .032(.813) .026(.660) .050(1.27) TYP ...
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... No licenses to patents or other intellectual prop- erty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. ...