K4S161622H-UC60 Samsung Semiconductor, K4S161622H-UC60 Datasheet - Page 11

• Manufacturer Part Number: K4S161622H-UC60
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S161622H-UC60

• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 150mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

SDRAM 16Mb H-die(x16)
SIMPLIFIED TRUTH TABLE
Note :
Register
Refresh
Bank Active & Row Addr.
Read &
Column Address
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power Down Mode
DQM
No Operation Command
1. OP Code : Operand Code
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA : Bank select address.
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
A
A new command can be issued after 2 clock cycle of MRS.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at t
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
0
~ A
10
/AP is "High" at row precharge, BA is ignored and both banks are selected.
10
COMMAND
/AP, BA : Program keys. (@MRS)
Mode Register Set
Auto Refresh
Self
Refresh
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
Bank Selection
Both Banks
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1
H
H
H
H
H
H
H
H
H
H
H
L
L
L
CKEn
X
H
H
X
X
X
X
X
H
H
X
L
L
L
RP
CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
X
L
L
L
after the end of burst.
RAS
H
X
H
H
H
X
V
X
X
H
X
V
X
X
H
L
L
L
L
CAS
H
H
H
H
H
H
L
L
X
L
L
X
V
X
X
X
V
X
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
WE
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
Rev. 1.5 August 2004
BA
V
V
V
V
X
CMOS SDRAM
A
OP CODE
10
Row Address
H
H
H
L
L
L
/AP
X
X
X
X
X
X
X
Address
Address
A
Column
Column
9
~ A
X
0
Note
1, 2
4, 5
4, 5
3
3
3
3
4
4
6
7