5962-9759801QYA Cypress Semiconductor Corp, 5962-9759801QYA Datasheet

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5962-9759801QYA

Manufacturer Part Number
5962-9759801QYA
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of 5962-9759801QYA

Memory Type
Flash
# Macrocells
128
Number Of Usable Gates
3200
Propagation Delay Time
20ns
Number Of Logic Blocks/elements
8
# I/os (max)
64
Operating Supply Voltage (typ)
5V
In System Programmable
Yes
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-55C to 125C
Operating Temperature Classification
Military
Mounting
Surface Mount
Pin Count
84
Package Type
CLCC
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
5962-9759801QYA
Manufacturer:
CYP
Quantity:
5 510
Part Number:
5962-9759801QYA
Quantity:
5 510
Part Number:
5962-9759801QYA
Manufacturer:
CYP
Quantity:
86
Cypress Semiconductor Corporation
Document #: 38-03031 Rev. *A
Features
Selection Guide
Maximum Propagation Delay
Minimum Set-up, t
Maximum Clock to Output
Typical Supply Current, I
Note:
Logic Block Diagram
• 128 macrocells in eight logic blocks
• 64 I/O pins
• Five dedicated inputs including four clock pins
• In-System Reprogrammable™ (ISR™) Flash technology
• Bus Hold capabilities on all I/Os and dedicated inputs
• No hidden delays
• High speed
• Fully PCI-compliant
• 3.3V or 5.0V I/O operation
• Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
• Pin-compatible with the CY7C373i
1. The 3.3V I/O mode timing adder, t
— JTAG interface
— f
— t
— t
— t
TQFP packages
MAX
PD
S
CO
= 5.5 ns
= 10 ns
= 6.5 ns
= 125 MHz
I/O
I/O
S
I/O
I/O
16
24
8
0
–I/O
–I/O
–I/O
–I/O
CC
15
23
31
[1]
7
[1]
, t
8 I/Os
8 I/Os
8 I/Os
8 I/Os
, t
3.3IO
CO
PD
, must be added to this specification when V
7C374i–125 7C374i–100 7C374i–83 7C7374iL–83 7C374i–66 7C374iL–66 Unit
125
5.5
6.5
10
BLOCK
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
LOGIC
4
32
C
D
A
B
UltraLogic™ 128-Macrocell Flash CPLD
MACROCELL
3901 North First Street
INPUT
125
12
6
7
36
16
36
16
36
16
36
16
Inputs
1
PIM
Functional Description
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
all members of the F
designed to bring the ease of use as well as PCI Local Bus
Specification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ F
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISR
because of the superior routability of the F
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
LASH
CCIO
125
15
Inputs
Clock
8
8
= 3.3V.
370i™ family of high-density, high-speed CPLDs. Like
4
36
16
36
16
36
16
36
16
INPUT/CLOCK
MACROCELLS
San Jose
BLOCK
LOGIC
BLOCK
BLOCK
BLOCK
LOGIC
LOGIC
LOGIC
32
H
15
75
G
F
E
8
8
4
LASH
,
CA 95134
LASH
370i family, the CY7C374i is
8 I/Os
8 I/Os
8 I/Os
8 I/Os
125
20
10
10
370i devices, the CY7C374i
I/O
I/O
I/O
I/O
Revised April 19, 2004
56
48
40
32
–I/O
–I/O
–I/O
–I/O
LASH
EN
CY7C374i
63
55
47
39
408-943-2600
20
10
10
75
). Additionally,
370i devices,
mA
ns
ns
ns

Related parts for 5962-9759801QYA

5962-9759801QYA Summary of contents

Page 1

... Typical Supply Current Note: 1. The 3.3V I/O mode timing adder must be added to this specification when V 3.3IO Cypress Semiconductor Corporation Document #: 38-03031 Rev. *A UltraLogic™ 128-Macrocell Flash CPLD Functional Description The CY7C374i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the F 370i™ ...

Page 2

Pin Configurations I/O I/O I/O /SCLK 10 I/O I/O I/O I/O I/O CLK 0 V GND CLK 1 I/O I/O I/O I/O I/O I/O I/O I/O GND L I/O K I/O J I/O H I/O CLK1 G F I/O E ...

Page 3

Pin Configurations (continued) 100 1 SCLK GND CLK / CCIO ...

Page 4

Functional Description The logic blocks in the F 370i architecture are connected LASH with an extremely fast and predictable routing resource—the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the inter- connect. Like ...

Page 5

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC ...

Page 6

Capacitance Parameter Description [11, 12] C Input Capacitance I/O C Clock Signal Capacitance CLK [9] Inductance Parameter Description L Maximum Pin Inductance [9] Endurance Characteristics Parameter Description N Maximum Reprogramming Cycles AC Test Loads and Waveforms 238Ω (COM'L) 319Ω ...

Page 7

Switching Characteristics Over the Operating Range Parameter Description Combinatorial Mode Parameters t Input to Combinatorial Output PD t Input to Output Through Transparent Input or PDL [1] Output Latch t Input to Output Through Transparent Input and PDLL [1] Output ...

Page 8

Switching Characteristics Over the Operating Range (continued) Parameter Description Reset/Preset Parameters t Asynchronous Reset Width RW t Asynchronous Reset Recovery Time RR t Asynchronous Reset to Output RO t Asynchronous Preset Width PW t Asynchronous Preset Recovery Time PR t ...

Page 9

Switching Waveforms (continued) Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE Document ...

Page 10

Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS Ordering Information Speed (MHz) Ordering Code 125 CY7C374i–125AC CY7C374i–125JC 100 CY7C374i–100AC CY7C374i–100JC CY7C374i–100AI CY7C374i–100JI 83 CY7C374i–83AC CY7C374i–83JC CY7C374i–83AI CY7C374i–83JI CY7C374i–83GMB CY7C374i–83YMB ...

Page 11

Ordering Information Speed (MHz) Ordering Code 66 CY7C374i–66AC CY7C374i–66JC CY7C374i–66AI CY7C374i–66JI CY7C374i–66GMB CY7C374i–66YMB CY7C374iL–66AC CY7C374iL–66JC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...

Page 12

Package Diagrams Document #: 38-03031 Rev. *A 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 CY7C374i 51-85048-*B Page ...

Page 13

Package Diagrams (continued) Document #: 38-03031 Rev. *A 84-Pin Grid Array (Cavity Up) G84 84-Lead Plastic Leaded Chip Carrier J83 CY7C374i 51-80015-*A 51-85006-*A Page ...

Page 14

... Document #: 38-03031 Rev. *A © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 15

Document History Page Document Title: CY7C374i UltraLogic™ 128-Macrocell Flash CPLD Document Number: 38-03031 REV. ECN NO. Issue Date ** 106376 07/11/01 *A 213375 See ECN Document #: 38-03031 Rev. *A Orig. of Change SZV Changed from Spec number: 38-00496 to ...

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