CY37032P44-154JI Cypress Semiconductor Corp, CY37032P44-154JI Datasheet - Page 6

• Manufacturer Part Number: CY37032P44-154JI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY37032P44-154JI

• Family Name: Ultra 37000
• # Macrocells: 32
• Number Of Usable Gates: 960
• Frequency (max): 154MHz
• Propagation Delay Time: 7.5ns
• Number Of Logic Blocks/elements: 2
• # I/os (max): 37
• Operating Supply Voltage (typ): 5V
• In System Programmable: Yes
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03007 Rev. *E
Clocking
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
Product Term Clocking
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
POLARITY INPUT
FROM CLOCK
CLOCK PINS
INPUT/CLOCK PIN
0
1
2
3
C8 C9
POLARITY MUXES
FROM CLOCK
O
D
D
LE
0
1
2
3
C10
Q
Q
INPUT PIN
C11
O
Figure 4. Input/Clock Macrocell
Figure 3. Input Macrocell
D
Q
D
D
LE
Q
Q
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used.
Figure 5 illustrates the true timing model for the 167-MHz
devices in high speed mode. For combinatorial paths, any
input to any output incurs a 6.5-ns worst-case delay regardless
of the amount of logic used. For synchronous systems, the
input set-up time to the output macrocells for any input is 3.5
ns and the clock to output time is also 4.0 ns. These measure-
ments are for any output and synchronous clock, regardless
of the logic used.
The Ultra37000 features:
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
• No output bypass delays
0
1
C12
0
1
2
3
C10C11
O
O
D
TO PIM
Q
Ultra37000 CPLD Family
TO CLOCK MUX ON
ALL INPUT MACROCELLS
C13, C14, C15
0
1
2
3
C12 C13
0
1
O
O
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
OR C16
TO PIM
Page 6 of 64
TO CLOCK MUX
IN EACH
LOGIC BLOCK
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