CY7C006A-15JC Cypress Semiconductor Corp, CY7C006A-15JC Datasheet

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CY7C006A-15JC

Manufacturer Part Number
CY7C006A-15JC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C006A-15JC

Density
128Kb
Access Time (max)
15ns
Operating Supply Voltage (typ)
5V
Package Type
LCC
Operating Temp Range
0C to 70C
Supply Current
280mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
68
Word Size
8b
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C006A-15JC
Manufacturer:
ST
Quantity:
763
Part Number:
CY7C006A-15JC
Manufacturer:
CYP
Quantity:
1 348
Cypress Semiconductor Corporation
Document #: 38-06045 Rev. *C
Features
• True dual-ported memory cells which allow
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12
• Low operating power
• Fully asynchronous operation
Logic Block Diagram
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
A
A
CE
OE
R/W
SEM
BUSY
INT
1. See page 7 for Load Conditions.
2. I/O
3. BUSY is an output in master mode and an input in slave mode.
4. A
R/W
CE
OE
I/O
simultaneous access of the same memory location
— Active: I
— Standby: I
0L
0L
L
L
L
0L
0
L
–A
–A
L
–A
L
0
L
L
–I/O
–I/O
13/14L
13/14L
L
13
[3]
for 16K; A
7
7/8L
[4]
[4]
for x8 devices; I/O
[2]
CC
SB3
= 180 mA (typical)
0
–A
= 0.05 mA (typical)
14
14/15
for 32K devices.
8/9
0
–I/O
[1]
/15/20 ns
8
Address
for x9 devices.
Decode
14/15
3901 North First Street
Control
I/O
True Dual-Ported
Semaphore
RAM Array
Arbitration
Interrupt
M/S
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
• On-chip arbitration logic
• Semaphores included to permit software handshaking
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
Master/Slave chip select when using more than one
device
between ports
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
Control
I/O
San Jose
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
Address
Decode
14/15
CY7C006A/CY7C007A
CY7C016A/CY7C017A
CA 95134
14/15
8/9
Revised April 11, 2005
I/O
A
A
408-943-2600
0R
0R
0R
[3]
–A
–A
–I/O
BUSY
SEM
R/W
13/14R
13/14R
R/W
[2]
INT
CE
OE
OE
CE
7/8R
R
R
R
[4]
R
R
R
R
R
R
[4]

Related parts for CY7C006A-15JC

CY7C006A-15JC Summary of contents

Page 1

... Semaphores included to permit software handshaking between ports • INT flags for port-to-port communication • Pin select for Master or Slave • Commercial temperature range • Available in 68-pin PLCC (CY7C006A, CY7C007A and CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin TQFP (CY7C007A and CY7C016A) I/O I/O ...

Page 2

... CC NC GND I/O 0R I I/O 3R I/O 4R I Notes: 5. This pin is I/O for CY7C017A only connect pin for 16K devices. 14 Document #: 38-06045 Rev. *C 68-Pin PLCC Top View CY7C006A (16K CY7C007A (32K CY7C017A (32K 80-Pin TQFP Top View CY7C007A (32K x 8) ...

Page 3

... Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for I (mA) (Both Ports TTL Level) SB1 Typical Standby Current for I (mA) (Both Ports CMOS Level) SB3 Document #: 38-06045 Rev. *C 64-Pin TQFP Top View CY7C006A (16K CY7C006A CY7C007A CY7C016A CY7C017A [1] -12 12 195 55 0 ...

Page 4

... An automatic power-down feature is controlled independently on each port by a Chip Select (CE) pin. The CY7C006A, CY7C007A, and CY7C017A are available in 68-pin PLCC packages, the CY7C006A is also available in 64-pin TQFP, and the CY7C007A and CY7C016A are also available in 80-pin TQFP packages. Write Operation Data must be set up for a duration R/W in order to guarantee a valid write ...

Page 5

... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C006A, CY7C007A, CY7C016A and CY7C017A provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within t PS logic will determine which port has access ...

Page 6

... Ind. [8, 9] Test Conditions ° MHz 5.0V CC CY7C006A/CY7C007A CY7C016A/CY7C017A [8] .........................................–0.5V to +7.0V Ambient Temperature ° ° 5V ± 10 +70 C CY7C006A CY7C007A CY7C016A CY7C017A -15 -20 Min. Typ. Max. Min. Typ. Max. 2.4 2.4 0.4 2.2 2.2 0.8 –10 10 –10 190 280 180 215 ...

Page 7

... Test Conditions pF. Document #: 38-06045 Rev 250Ω TH OUTPUT (b) Thévenin Equivalent (Load 1) [11] 3.0V GND ≤ Capacitance (pF) (b) Load Derating Curve CY7C006A/CY7C007A CY7C016A/CY7C017A 893Ω OUTPUT 1.4V (c) Three-State Delay (Load 2) (Used for HZWE including scope and jig) ALL INPUT PULSES 90% 90% 10% 10% ≤ ...

Page 8

... For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. Test conditions used are Load 2. 19. For 15 ns industrial parts t Min. is 0.5 ns. HD Document #: 38-06045 Rev. *C CY7C006A/CY7C007A CY7C016A/CY7C017A [12] CY7C006A CY7C007A CY7C016A CY7C017A [1] –12 –15 Min. Max. ...

Page 9

... SEM Address Access Time SAA Data Retention Mode The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, ...

Page 10

... ADDRESS CE DATA OUT Notes: 25. Address valid prior to or coincident with CE transition LOW. 26. To access RAM SEM = access semaphore Document #: 38-06045 Rev. *C [22, 25, 26] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C006A/CY7C007A CY7C016A/CY7C017A t HZCE t HZOE DATA VALID OHA t HZCE Page ...

Page 11

... PWE [32] t HZWE t SD [27, 28, 29, 34 SCE LOW CE or SEM. PWE . HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be CY7C006A/CY7C007A CY7C016A/CY7C017A [32] t HZOE LZWE NOTE allow the I/O drivers to turn off and data ...

Page 12

... SPS Document #: 38-06045 Rev. *C [35 SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE [36, 37, 38] MATCH t SPS MATCH = CE = HIGH CY7C006A/CY7C007A CY7C016A/CY7C017A OHA VALID ADRESS t ACE DATA VALID OUT t DOE READ CYCLE Page ...

Page 13

... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 39 LOW Document #: 38-06045 Rev. *C [39 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C006A/CY7C007A CY7C016A/CY7C017A BHA t BDD t DDD VALID t WDD Page ...

Page 14

... BUSY will be asserted. PS Document #: 38-06045 Rev. *C [40] ADDRESS MATCH BLC ADDRESS MATCH BLC [40 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C006A/CY7C007A CY7C016A/CY7C017A t BHC t BHC Page ...

Page 15

... OE L INT L Notes: 41. t depends on which enable pin ( depends on which enable pin (CE INS INR Document #: 38-06045 Rev WRITE 7FFF [41 [42] t INR t WC WRITE 7FFE [41 [42] t INR ) is deasserted first R asserted last CY7C006A/CY7C007A CY7C016A/CY7C017A t RC READ 7FFF t RC READ 7FFE Page ...

Page 16

... No change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C006A/CY7C007A CY7C016A/CY7C017A Operation Right Port R 0R–14R ...

Page 17

... Ordering Information 16K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C006A-12AC CY7C006A-12JC 15 CY7C006A-15AC CY7C006A-15JC 20 CY7C006A-20AC CY7C006A-20JC 32K x8 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C007A-12AC CY7C007A-12JC 15 CY7C007A-15AC CY7C007A-15JC 20 CY7C007A-20AC CY7C007A-20JC 16K x9 Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 12 CY7C016A-12AC 15 CY7C016A-15AC 20 CY7C016A-20AC ...

Page 18

... Package Diagrams 64-Lead Thin Plastic Quad Flat Pack ( 1.4 mm) A65 Document #: 38-06045 Rev. *C CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85046-*B Page ...

Page 19

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 80-Pin Thin Plastic Quad Flat Pack A80 68-Lead Plastic Leaded Chip Carrier J81 CY7C006A/CY7C007A CY7C016A/CY7C017A 51-85065-*B 51-85005-*A ...

Page 20

... Document History Page Document Title: CY7C006A/CY7C007A/CY7C016A/CY7C017A 32K/16K x 8, 32K/16K x 9 Dual Port Static RAM Document Number: 38-06045 Issue REV. ECN NO. Date ** 110197 09/29/01 *A 122295 12/27/02 *B 237620 See ECN *C 345376 See ECN Document #: 38-06045 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-00831 to 38-06045 ...

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