CY7C4245-10JC Cypress Semiconductor Corp, CY7C4245-10JC Datasheet

CY7C4245-10JC

Manufacturer Part Number

CY7C4245-10JC

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY7C4245-10JC.pdf (25 pages)

Specifications of CY7C4245-10JC

Density

64Kb

Word Size

18b

Sync/async

Synchronous

Expandable

Yes

Package Type

LCC

Operating Supply Voltage (typ)

Operating Supply Voltage (min)

4.5V

Operating Supply Voltage (max)

5.5V

Operating Temp Range

0C to 70C

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

Lead Free Status / Rohs Status

Not Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

CY7C4245-10JC

Manufacturer:

CYPRESS

Quantity:

1 310

Current page: 1 of 25
Download datasheet (412Kb)

Features

Functional Description

(FIFO) memories with clocked read and write interfaces. All

are 18 bits wide and are pin/functionally compatible to

IDT722x5. The CY7C42X5 can be cascaded to increase FIFO

depth. Programmable features include Almost Full/Almost

Empty flags. These FIFOs provide solutions for a wide variety

of data buffering needs, including high-speed data acquisition,

multiprocessor interfaces, and communications buffering.

These FIFOs have 18-bit input and output ports that are con-

trolled by separate clock and enable signals. The input port is

Cypress Semiconductor Corporation

• High-speed, low-power, first-in first-out (FIFO)

• 64 x 18 (CY7C4425)

• 256 x 18 (CY7C4205)

• 512 x 18 (CY7C4215)

• 1K x 18 (CY7C4225)

• 2K x 18 (CY7C4235)

• 4K x 18 (CY7C4245)

• High-speed 100-MHz operation (10 ns read/write cycle

• Low power (I

• Fully asynchronous and simultaneous read and write

• Empty, Full, Half Full, and Programmable Almost

• TTL-compatible

• Retransmit function

• Output Enable (OE) pin

• Independent read and write enable pins

• Center power and ground for reduced noise

• Supports free-running 50% duty cycle clock inputs

• Width Expansion Capability

• Depth Expansion Capability

• Space saving 64-pin 10x10 TQFP, and 14x14 TQFP

• 68-pin PLCC

he CY7C42X5 are high-speed, low-power, first-in first-out

memories

time)

operation

Empty/Almost Full status flags

=45 mA)

64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs

•

3901 North First Street

controlled by a free-running clock (WCLK) and a write enable

pin (WEN).

When WEN is asserted, data is written into the FIFO on the

rising edge of the WCLK signal. While WEN is held active, data

is continually written into the FIFO on each cycle. The output

port is controlled in a similar manner by a free-running read

clock (RCLK) and a read enable pin (REN). In addition, the

CY7C42X5 have an output enable pin (OE). The read and

write clocks may be tied together for single-clock operation or

the two clocks may be run independently for asynchronous

read/write applications. Clock frequencies up to 100 MHz are

achievable.

Retransmit and Synchronous Almost Full/Almost Empty flag

features are available on these devices.

Depth expansion is possible using the cascade input (WXI,

RXI), cascade output (WXO, RXO), and First Load (FL) pins.

The WXO and RXO pins are connected to the WXI and RXI

pins of the next device, and the WXO and RXO pins of the last

device should be connected to the WXI and RXI pins of the

first device. The FL pin of the first device is tied to V

FL pin of all the remaining devices should be tied to V

The CY7C42X5 provides five status pins. These pins are de-

coded to determine one of five states: Empty, Almost Empty,

Half Full, Almost Full, and Full (see Table 2 ). The Half Full flag

shares the WXO pin. This flag is valid in the standalone and

width-expansion configurations. In the depth expansion, this

pin provides the expansion out (WXO) information that is used

to signal the next FIFO when it will be activated.

The Empty and Full flags are synchronous, i.e., they change

state relative to either the read clock (RCLK) or the write clock

(WCLK). When entering or exiting the Empty states, the flag is

updated exclusively by the RCLK. The flag denoting Full states

is updated exclusively by WCLK. The synchronous flag archi-

tecture guarantees that the flags will remain valid from one

clock cycle to the next. As mentioned previously, the Almost

Empty/Almost Full flags become synchronous if the

using an advanced 0.65

ESD protection is greater than 2001V, and latch-up is prevent-

ed by the use of guard rings.

/SMODE is tied to V

•

San Jose

CY7C4425/4205/4215

CY7C4225/4235/4245

April 1995 - Revised August 18, 1997

•

. All configurations are fabricated

N-Well CMOS technology. Input

CA 95134

•

fax id: 5410

408-943-2600

and the

Related parts for CY7C4245-10JC

CY7C4245-10JC Summary of contents

Page 1

... High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4425) • 256 x 18 (CY7C4205) • 512 x 18 (CY7C4215) • (CY7C4225) • (CY7C4235) • (CY7C4245) • High-speed 100-MHz operation (10 ns read/write cycle time) • Low power (I =45 mA) CC • Fully asynchronous and simultaneous read and write operation • ...

Page 2

... GND 42x5–2 2 CY7C4425/4205/4215 CY7C4225/4235/4245 FLAG PROGRAM REGISTER FF EF FLAG PAE LOGIC PAF SMODE READ POINTER READ CONTROL 42X5–1 RCLK REN TQFP Top View CY7C4425 43 6 CY7C4205 42 7 CY7C4215 41 8 CY7C4225 40 9 CY7C4235 CY7C4245 GND GND GND 42X5–3 ...

Page 3

... SS mode by strobing RT. I Cascaded - Connected to WXO of previous device. Not Cascaded - Tied CY7C4425/4205/4215 CY7C4225/4235/4245 7C42X5-25 7C42X5- CY7C4235 CY7C4245 68-pin PLCC 68-pin PLCC 64-pin TQFP 64-pin TQFP (10x10/14x14) (10x10/14x14) Function /SMODE is tied CC /SMODE is tied /SMODE is tied to CC /SMODE is tied are written (read) into (from) the programma- ...

Page 4

Pin Definitions (continued) Signal Name Description I/O RXI Read Expansion Input RXO Read Expansion Output RS Reset OE Output Enable V /SMODE Synchronous CC Almost Empty/ Almost Full Flags Maximum Ratings (Above which the useful life may be impaired. For ...

Page 5

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT AC Test Loads and Waveforms R11.1K 5V OUTPUT C L INCLUDING JIG AND SCOPE Equivalent to: THÉ EVENIN EQUIVALENT 410 OUTPUT Notes: 7. Tested initially and after any ...

Page 6

Switching Characteristics Over the Operating Range (continued) Parameter Description t Clock to Programmable Almost-Full Flag PAFsynch (Synchronous mode Clock to Programmable Almost-Empty Flag PAEasynch (Asynchronous mode Clock to Programmable Almost-Full Flag PAEsynch (Synchronous mode, V ...

Page 7

Switching Waveforms (continued) Read Cycle Timing RCLK t t ENS ENH REN EF Q – OLZ OE WCLK WEN [15] Reset Timing RS REN, WEN, LD EF,PAE FF,PAF Notes: 14. .t ...

Page 8

Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLK –D D (FIRSTVALID WRITE ENS WEN t SKEW2 RCLK EF REN Q – Empty Flag ...

Page 9

Switching Waveforms (continued) Full Flag Timing NO WRITE WCLK [13] t SKEW1 D – WFF FF WEN RCLK t ENS REN LOW OE Q –Q DATA IN OUTPUT REGISTER 0 17 Half-Full Flag Timing t CLKH WCLK ...

Page 10

Switching Waveforms (continued) Programmable Almost Empty Flag Timing t CLKH WCLK WEN [19] ] PAE RCLK REN Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW) t CLKH WCLK WEN WEN2 PAE t SKEW3 RCLK REN Notes: ...

Page 11

... PAF offset = m. Number of data words written into FIFO already = 64 – for the CY7C4425, 256 – for the CY7C4205, 512 – for the CY7C4215. 1024 – for the CY7C4225, 2048 – for the CY7C4235, and 4096 – for the CY7C4245. 24. PAF is offset = m. ...

Page 12

Switching Waveforms (continued) Write Programmable Registers t CLK t CLKH WCLK t ENS LD t ENS WEN – Read Programmable Registers t CLK t CLKH RCLK t ENS LD t ENS WEN Q –Q 0 ...

Page 13

Switching Waveforms (continued) Read Expansion Out Timing t WCLK RXO t ENS REN Write Expansion In Timing WXI WCLK Read Expansion In Timing RXI RCLK [33, 34, 35] Retransmit Timing FL/RT REN/WEN EF/FF and all async flags HF/PAE/PAF Notes: 32. ...

Page 14

Architecture The CY7C42X5 consists of an array words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, ...

Page 15

Flags are governed by the relative loca- tions of the read and write pointers and ...

Page 16

Depth Expansion Configuration (with Programmable Flags) The CY7C42X5 can easily be adapted to applications requir- ing more than 64/256/512/1024/2048/4096 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maxi- mum depth is limited only by signal loading. Follow ...

Page 17

Typical AC and DC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 V =3. =25 C 0.8 A f=100 MHz 0 4.5 5.5 SUPPLY VOLTAGE (V) NORMALIZED t vs.SUPPLY A VOLTAGE 1.2 T =25 ...

Page 18

Ordering Information Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4425-10AC CY7C4425-10ASC CY7C4425-10JC CY7C4425-10AI CY7C4425-10ASI CY7C4425-10JI 15 CY7C4425-15AC CY7C4425-15ASC CY7C4425-15JC CY7C4425-15AI CY7C4425-15ASI CY7C4425-15JI 25 CY7C4425-25AC CY7C4425-25ASC CY7C4425-25JC CY7C4425-25AI CY7C4425-25ASI CY7C4425-25JI 35 CY7C4425-35AC CY7C4425-35ASC CY7C4425-35JC CY7C4425-35AI CY7C4425-35ASI CY7C4425-35JI Package ...

Page 19

Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4205-10AC CY7C4205-10ASC CY7C4205-10JC CY7C4205-10AI CY7C4205-10ASI CY7C4205-10JI 15 CY7C4205-15AC CY7C4205-15ASC CY7C4205-15JC CY7C4205-15AI CY7C4205-15ASI CY7C4205-15JI 25 CY7C4205-25AC CY7C4205-25ASC CY7C4205-25JC CY7C4205-25AI CY7C4205-25ASI CY7C4205-25JI 35 CY7C4205-35AC CY7C4205-35ASC CY7C4205-35JC CY7C4205-35AI CY7C4205-35ASI CY7C4205-35JI Package Package Name ...

Page 20

Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4215-10AC CY7C4215-10ASC CY7C4215-10JC CY7C4215-10AI CY7C4215-10ASI CY7C4215-10JI 15 CY7C4215-15AC CY7C4215-15ASC CY7C4215-15JC CY7C4215-15AI CY7C4215-15ASI CY7C4215-15JI 25 CY7C4215-25AC CY7C4215-25ASC CY7C4215-25JC CY7C4215-25AI CY7C4215-25ASI CY7C4215-25JI 35 CY7C4215-35AC CY7C4215-35ASC CY7C4215-35JC CY7C4215-35AI CY7C4215-35ASI CY7C4215-35JI Package Package Name ...

Page 21

Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4225-10AC CY7C4225-10ASC CY7C4225-10JC CY7C4225-10AI CY7C4225-10ASI CY7C4225-10JI 15 CY7C4225-15AC CY7C4225-15ASC CY7C4225-15JC CY7C4225-15AI CY7C4225-15ASI CY7C4225-15JI 25 CY7C4225-25AC CY7C4225-25ASC CY7C4225-25JC CY7C4225-25AI CY7C4225-25ASI CY7C4225-25JI 35 CY7C4225-35AC CY7C4225-35ASC CY7C4225-35JC CY7C4225-35AI CY7C4225-35ASI CY7C4225-35JI Package Package Name ...

Page 22

Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4235-10AC CY7C4235-10ASC CY7C4235-10JC CY7C4235-10AI CY7C4235-10ASI CY7C4235-10JI 15 CY7C4235-15AC CY7C4235-15ASC CY7C4235-15JC CY7C4235-15AI CY7C4235-15ASI CY7C4235-15JI 25 CY7C4235-25AC CY7C4235-25ASC CY7C4235-25JC CY7C4235-25AI CY7C4235-25ASI CY7C4235-25JI 35 CY7C4235-35AC CY7C4235-35ASC CY7C4235-35JC CY7C4235-35AI CY7C4235-35ASI CY7C4235-35JI Package Package Name ...

Page 23

... Synchronous FIFO Speed (ns) Ordering Code 10 CY7C4245-10AC CY7C4245-10ASC CY7C4245-10JC CY7C4245-10AI CY7C4245-10ASI CY7C4245-10JI 15 CY7C4245-15AC CY7C4245-15ASC CY7C4245-15JC CY7C4245-15AI CY7C4245-15ASI CY7C4245-15JI 25 CY7C4245-25AC CY7C4245-25ASC CY7C4245-25JC CY7C4245-25AI CY7C4245-25ASI CY7C4245-25JI 35 CY7C4245-35AC CY7C4245-35ASC CY7C4245-35JC CY7C4245-35AI CY7C4245-35ASI CY7C4245-35JI Package Package Name Type A65 64-Lead 14x14 Thin Quad Flatpack A64 64-Lead 10x10 Thin Quad Flatpack ...

Page 24

Package Diagrams 64-Lead Thin Plastic Quad Flat Pack A65 64-Pin Thin Quad Flat Pack A64 24 CY7C4425/4205/4215 CY7C4225/4235/4245 ...

Page 25

... Plastic Leaded Chip Carrier J81 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

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