79RC32V334-150BB IDT, Integrated Device Technology Inc, 79RC32V334-150BB Datasheet

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Features ◆ RC32300 32-bit Microprocessor – 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture (ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions – Supports big or little endian operation – MMU with 32 ...

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IDT 79RC32334—Rev. Y ◆ 4 DMA Channels – 4 general purpose DMA, each with endianess swappers and byte lane data alignment – Supports scatter/gather, chaining via linked lists of records – Supports memory-to-memory, memory-to-I/O, memory-to- PCI, PCI-to-PCI, and I/O-to-I/O transfers ...

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IDT 79RC32334—Rev. Y ◆ 2KB of 2-way set associative data cache, capable of write-back and write-through operation. ◆ Cache locking per line to speed real-time systems and critical system functions ◆ On-chip TLB to enable multi-tasking in modern operating systems ...

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IDT 79RC32334—Rev. Y Packaging The RC32334 is packaged using a 256-lead PBGA package, with 1.0mm ball spacing. Thermal Considerations The RC32334 consumes less than 2.1 W peak power. The device is guaranteed in an ambient temperature range of 0° to ...

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IDT 79RC32334—Rev. Y Pin Description Table The following table lists the pins provided on the RC32334. Note that those pin names followed by ”_n” are active-low signals. All external pull-ups and pull-downs require 10 kΩ resistor. Reset Name Type State ...

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IDT 79RC32334—Rev. Y Reset Name Type State Strength Capability Status mem_we_n[3:0] Output H mem_wait_n Input mem_245_oe_n Output H mem_245_dt_r_n Output Z output_clk Output cpu_mas terclk PCI Interface pci_ad[31:0] I/O Z pci_cbe_n[3:0] I/O Z pci_par I/O Z pci_frame_n I/O Z pci_trdy_n ...

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IDT 79RC32334—Rev. Y Reset Name Type State Strength Capability Status pci_rst_n Input L pci_devsel_n I/O Z pci_req_n[2] Input Z pci_req_n[1] Input Z pci_req_n[0] I pci_gnt_n[2] Output Z pci_gnt_n[1] / I/O X for 1 pci pci_eeprom_cs clock then 2 ...

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IDT 79RC32334—Rev. Y Reset Name Type State Strength Capability Status sdram_cas_n Output H sdram_we_n Output H sdram_cke Output H sdram_cs_n[3:0] Output H sdram_s_n[1:0] Output H sdram_bemask_n Output H [3:0] sdram_245_oe_n Output H sdram_245_dt_r_n Output Z On-Chip Peripherals dma_ready_n[1:0] / I/O ...

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IDT 79RC32334—Rev. Y Reset Name Type State Strength Capability Status uart_tx[1:0] I/O Z uart_cts_n[0] I/O Z uart_dsr_n[0] uart_dtr_n[0] uart_rts_n[0] spi_mosi I/O L spi_miso I/O Z spi_sck I/O L spi_ss_n I/O H CPU Core Specific Signals cpu_nmi_n Input cpu_masterclk Input cpu_int_n[5:4], ...

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IDT 79RC32334—Rev. Y Reset Name Type State Strength Capability Status cpu_dt_r_n Output Z JTAG Interface Signals jtag_tck Input jtag_tdi, Input ejtag_dint_n jtag_tdo, Output Z ejtag_tpc jtag_tms Input jtag_trst_n Input L ejtag_dclk Output Z ejtag_pcst[2:0] I/O Z ejtag_debugboot Input external pull- ...

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IDT 79RC32334—Rev. Y Reset Name Type State Status Debug Signals debug_cpu_dma_n I/O Z debug_cpu_ack_n I/O Z debug_cpu_ads_n I/O Z debug_cpu_i_d_n I/O Z Mode Bit Settings to Configure Controller on Reset The following table lists the mode bit settings to configure ...

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IDT 79RC32334—Rev. Y Pin Mode Bit mem_addr[19:18] 9:8 MSB (9) reset_boot_mode Settings By using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_0000 to base 1900_0000, as required. The RC32334 cold ...

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IDT 79RC32334—Rev. Y Logic Diagram — RC32334 cpu_masterclk cpu_coldreset_n cpu_nmi_n cpu_int_n[5:4],[2:0] cpu_dt_r_n pci_cbe_n[3:0] pci_ad[31:0] pci_par pci_frame_n pci_trdy_n pci_irdy_n pci_stop_n pci_idsel pci_perr_n pci_serr_n pci_clk pci_rst_n pci_devsel_n pci_req_n[2:0] pci_gnt_n[2:0] pci_inta_n pci_lock_n pci_eeprom_mdi pci_eeprom_mdo pci_eeprom_cs pci_eeprom_sk jtag_tck jtag_tms jtag_tdi jtag_tdo jtag_trst_n debug_cpu_dma_n debug_cpu_ack_n ...

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IDT 79RC32334—Rev. Y Clock Parameters — RC32334 (Ta = 0°C to +70°C Commercial -40°C to +85°C Industrial, V Parameter cpu_masterclock HIGH t MCHIGH cpu_masterclock LOW t MCLOW 1 cpu_masterclock period t MCP 2 cpu_masterclock Rise & Fall Time ...

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IDT 79RC32334—Rev. Y Power Ramp-up There is no special requirement for how fast Vcc and VccP ramp up to 3.3V. However, all timing references are based on Vcc and VccP stabilized at 3.3V -5%. AC Timing Characteristics — RC32334 (Ta ...

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IDT 79RC32334—Rev. Y Signal pci_eeprom_mdi pci_eeprom_mdo, pci_eeprom_cs pci_eeprom_sk pci_ad[31:0], pci_cbe_n[3:0], pci_par, pci_frame_n, pci_trdy_n, pci_irdy_n, pci_stop_n, pci_perr_n, pci_serr_n, pci_devsel_n pci_req_n[0], pci_gnt_[2], pci_gnt_n[1], pci_gnt_n[0], pci_inta_n SDRAM Controller sdram_245_dt_r_n sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], sdram_s_n[1:0], sdram_bemask_n[3:0], sdram_cke sdram_addr_12 sdram_245_oe_n sdram_245_dt_r_n sdram_ras_n, sdram_cas_n, sdram_we_n, sdram_cs_n[3:0], ...

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IDT 79RC32334—Rev. Y Signal UARTs uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] uart_rx[1:0], uart_tx[1:0], uart_cts_n[0], uart_dsr_n[0], uart_dtr_n[0], uart_rts_n[0] SPI Interface spi_clk, spi_mosi, spi_miso spi_clk, spi_mosi, spi_miso spi_clk, spi_mosi, spi_miso ...

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IDT 79RC32334—Rev. Y Signal EJTAG Interface ejtag_tms, ejtag_debugboot ejtag_tms, ejtag_debugboot jtag_tdo Output Delay Time jtag_tdi Input Setup Time jtag_tdi Input Hold Time jtag_trst_n Low Time jtag_trst_n Removal Time ejtag_tpc Output Delay Time ejtag_pcst Output Delay Time 1. At all pipeline ...

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IDT 79RC32334—Rev. Y — Standard EJTAG Timing Figure 4 represents the timing diagram for the EJTAG interface signals. The standard JTAG connector is a 10-pin connector providing 5 signals and 5 ground pins. For Standard EJTAG, a 24-pin connector has ...

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IDT 79RC32334—Rev. Y Output Loading for AC Testing Note: PCI pins have been correlated to PCI 2.2. Recommended Operation Temperature and Supply Voltage Grade Temperature Commercial 0°C to +70°C (Ambient) Industrial -40°C to +85°C (Ambient) DC Electrical Characteristics — RC32334 ...

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IDT 79RC32334—Rev. Y Parameter Minimum PCI Drive V — OL Output V — OH Pads V — — IH All Pads C — 5pF — — OUT I/O — LEAK ...

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IDT 79RC32334—Rev. Y Power Curves The following two graphs contain the simulated power curves that show power consumption at various bus frequencies. Note: Only pipeline frequencies that are integer multiples (2x, 3x, 4x) of bus frequencies are supported. 600.0 500.0 ...

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IDT 79RC32334—Rev. Y Absolute Maximum Ratings Symbol Vimin Tstg 1. Functional and tested operating conditions are given in Table 7. Absolute maximum ratings are stress ratings only, and functional operation is not guaranteed beyond recommended operating voltages ...

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IDT 79RC32334—Rev. Y Pin Function Alt Pin B9 sdram_addr_12 F9 B10 sdram_bemask_n[3] F10 B11 mem_addr[16] 1 F11 B12 mem_addr[20] 1 F12 B13 mem_data[11] F13 B14 cpu_coldreset_n F14 B15 mem_addr[25] F15 B16 mem_data[12] F16 C1 uart_rx[ uart_tx[0] 1 ...

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IDT 79RC32334—Rev. Y Pin Function Alt Pin D14 mem_data[17] H14 D15 mem_data[14] H15 D16 mem_data[18] H16 Function Alt Pin V P M14 cpu_nmi_n cc mem_data[27] M15 pci_ad[0] mem_data[4] M16 mem_data[21] Table 11 RC32334 256-pin PBGA Package Pin-Out (Part 3 of ...

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IDT 79RC32334—Rev. Y Pin Layout Vcc IO J Vcc Vss The lighter shaded area shows the ground pins (Vss) The darker ...

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IDT 79RC32334—Rev. Y RC32334 Alternate Signal Functions Pin Alt #1 Alt #2 A1 PIO[15] A6 sdram_addr[3] A7 sdram_addr[7] A8 sdram_addr[11] A11 sdram_addr[15] A12 modebit[9] A16 PIO[2] timer_gate_n[0] B1 PIO[12] B2 PIO[14] B6 sdram_addr[2] B7 sdram_addr[6] B8 sdram_addr[10] B11 sdram_addr[16] B12 ...

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IDT 79RC32334—Rev. Y RC32334 Package Drawing — 256-pin PBGA August 31, 2004 ...

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IDT 79RC32334—Rev. Y RC32334 Package Drawing — Page Two August 31, 2004 ...

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... Type 334 V = 3.3V ±5% 79RC32 = 32-bit family product Valid Combinations 79RC32V334 - 100BB, 133BB, 150BB 79RC32V334 - 100BBG, 133BBG, 150BBG 79RC32V334 - 100BBI, 133BBI, 150BBI 79RC32V334 - 100BBGI, 133BBGI, 150BBGI CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 SSS PP CPU Package Temp range/ ...