UPD75P3216GT Renesas Electronics America, UPD75P3216GT Datasheet - Page 26

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UPD75P3216GT

Manufacturer Part Number
UPD75P3216GT
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD75P3216GT

Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD75P3216GT
Manufacturer:
RENESAS
Quantity:
7 048
Part Number:
UPD75P3216GT
Manufacturer:
NEC
Quantity:
20 000
24
I/O
CPU control
Special
Interrupt
control
Instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBE to 15.
Group
2. TBR and TCALL instructions are assembler directives for the GETI instruction’s table definitions.
3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
EI
DI
IN
OUT
HALT
STOP
NOP
SEL
GETI
Mnemonic
Note 1
Note 1
Note 2, 3
IEXXX
IEXXX
A, PORTn
XA, PORTn
PORTn, A
PORTn, XA
RBn
MBn
taddr
Operand
No. of Machine
Bytes
2
2
2
2
2
2
2
2
2
2
1
2
2
1
1
Data Sheet U10241EJ1V1DS
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Cycle
2
2
2
2
2
2
2
2
2
2
1
2
2
3
3
4
3
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
IME(IPS.3)←1
IEXXX←1
IME(IPS.3)←0
IEXXX←0
A←PORTn
XA←PORTn+
PORTn←A
PORTn+
Set HALT Mode(PCC.2←1)
Set STOP Mode(PCC.3←1)
No Operation
RBS←n (n=0-3)
MBS←n (n=0, 1, 15)
• When using TBR instruction
• When using TCALL instruction
• When using instruction other than
• When using TBR instruction
• When using TCALL instruction
• When using instruction other than
(SP–6)(SP–3)(SP–4)←PC
PC
(SP–4)(SP–1)(SP–2)←PC
(SP+1)←MBE, RBE, PC
PC
SP←SP–4
TBR or TCALL
Execute (taddr)(taddr+1) instructions
PC
(SP–2)←X, X, MBE, RBE
PC
SP←SP–6
TBR or TCALL
Execute (taddr)(taddr+1) instructions
13-0
13-0
13-0
13-0
←(taddr)
←(taddr)
←(taddr)
←(taddr)
1
, PORTn←XA(n=8)
1
Operation
, PORTn(n=8)
5-0
5-0
5-0
5-0
+(taddr+1)
+(taddr+1)
+(taddr+1)
+(taddr+1)
(n=0-3, 5, 6, 8, 9)
(n=2-3, 5, 6, 8, 9)
13, 12
11-0
11-0
Addressing
Area
*10
*10
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
Determined by
referenced
instruction
Determined by
referenced
instruction
µ PD75P3216
Condition
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