SC1205CS.TR Semtech, SC1205CS.TR Datasheet - Page 7

• Manufacturer Part Number: SC1205CS.TR
• Manufacturer: Semtech

Specifications of SC1205CS.TR

• Number Of Drivers: 2
• Driver Configuration: Inverting/Non-Inverting
• Driver Type: High and Low Side
• Input Logic Level: CMOS/TTL
• Rise Time: 24ns
• Fall Time: 21ns
• Propagation Delay Time: 32ns
• Frequency (max): 1MHz
• Operating Supply Voltage (max): 6V
• Peak Output Current: 3A
• Power Dissipation: 660mW
• Output Resistance: 1.2/1Ohm
• Operating Supply Voltage (min): 4.15V
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 125C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 8
• Package Type: SOIC
• Lead Free Status / Rohs Status: Not Compliant

the SC1205 PGND pin and the Source of the bottom
FET must be very close to each other, preferably with
common PCB copper land with multiple vias to the ground
plane (if used). The parallel Schottky (if used) must be
physically next to the Bottom FET’s drain and source pins.
Any trace or lead inductance in these connections will
drive current way from the Schottky and allow it to flow
through the FET’s Body diode, thus reducing efficiency.
Preventing Inadvertent Bottom FET Turn-on
At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the Bot-
tom FET’s gate through the Miller capacitance, Crss of
the bottom FET. The voltage appearing on the gate due
to this spike is:
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous imped-
ance of the capacitors. (since dV/dT and thus the effec-
tive frequency is very high). If the BG pin of the SC1205
is very close to the bottom FET, Vspike will be reduced
depending on trace inductance, rate of rise of current,
etc.
While not shown in Figure 4, a capacitor may be added
from the gate of the Bottom FET to its source, preferably
less than .5” away. This capacitor will be added to Ciss
in the above equation to reduce the effective spike volt-
age.
The bottom MOSFET must be selected with attention
paid to the Crss/Ciss ratio. A low ratio reduces the Miller
feedback and thus reduces Vspike. Also MOSFETs with
higher Turn-on threshold voltages will conduct at a higher
voltage and will not turn on during the spike. The MOSFET
shown in the schematic (Figure 4) has a 2 volt threshold
and will require approximately 4.5 volts Vgs to be con-
ducting, thus reducing the possibility of shoot-through. A
zero ohm bottom FET gate resistor will obviously help
keeping the gate voltage low during off time.
Ultimately, slowing down the top FET by adding gate re-
sistance will reduce di/dt which will in turn make the ef-
fective impedance of the capacitors higher, thus allow-
ing the BG driver to hold the bottom gate voltage low. It
POWER MANAGEMENT
Applications Information (Cont.)
2004 Semtech Corp.
V
SPIKE
(
Crss
Vin
*
crss
ciss
7
does this at the expense of increased switching times
(and switching losses) for the top FET.
RINGING ON THE PHASE NODE
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is deter-
mined by:
to trace inductance of the connection between top FET’s
source and the bottom FET’s drain added to the trace
resistance of the bottom FET’s ground connection.
Coss=Drain to source capacitance of bottom FET. If there
is a Schottky used, the capacitance of the Schottky is
added to this value.
Although this ringing does not pose any power losses due
to a fairly high Q, it could cause the phase node to go too
far negative, thus causing improper operation, double
pulsing or at worst driver damage. On the SC1205, the
drain node, DRN, can go as far as 2V below ground with-
out affecting operation or sustaining damage.
The ringing is also an EMI nuisance due to its high reso-
nant frequency. Adding a capacitor, typically 1000-
2000pf, in parallel with Coss of the bottom FET can of-
ten eliminate the EMI issue. If double pulsing, due to
excessive ringing, placing a 4.7-10 ohm resistor between
the phase node and the DRN pin of the SC1205 should
eliminate the double pulsing.
The negative voltage spikes on the phase node adds to
the bootstrap capacitor voltage, thus increasing the volt-
age between VBST - VDRN. If the phase node negative
spikes are too large, the voltage on the boost capacitor
could exceed device’s absolute maximum rating of 7V.
To eliminate the effect of the ringing on the boost ca-
pacitor voltage, place a 4.7 - 10 Ohm resistor between
boost Schottky diode and Vcc to filter the negative spikes
on DRN Pin. Alternately, a Silicon diode, such as the
commonly available 1N4148 can substitute for the
Schottky diode and eliminate the need for the series re-
sistor.
L
Where:
st
= The effective stray inductance of the top FET added
Fring
2 (
*
Sqrt
L (
1
ST
*
Coss
SC1205
www.semtech.com
)