DS14C241WM National Semiconductor, DS14C241WM Datasheet - Page 5

• Manufacturer Part Number: DS14C241WM
• Manufacturer: National Semiconductor

Specifications of DS14C241WM

• Interface Circuit Standard 1: EIA/TIA-232-E/V.28
• Number Of Receivers: 5
• Number Of Transmitters: 4
• Number Of Transceivers: 4
• Data Transmission Topology: Point-to-Point
• Receiver Signal Type: Single-Ended
• Transmitter Signal Type: Single-Ended
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.5V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Supply Current: 10mA
• Power Supply Requirement: Single
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC W
• Lead Free Status / Rohs Status: Not Compliant

Parameter Measurement Information
Pin Descriptions
V
+5V (
V
Recommended external capacitor: C4 = 1.0 µF (6.3V). This
supply is not intended to be loaded externally.
V
Recommended external capacitor: C3 = 1.0 µF (16V). This
supply is not intended to be loaded externally.
C1
pins. Recommended capacitor — 1.0 µF (6.3V).
C2
pins. Recommended capacitor — 1.0 µF (16V).
EN (pin 24) — Controls the Receiver output TRI-STATE
Circuit. A HIGH level on this pin will disable the Receiver
Output.
SHUTDOWN (SD) (pin 25) — A High on the SHUTDOWN
pin will lower the total I
viding a low power state.
CC
+
−
+
+
(pin 17) — Negative supply for TIA/EIA-232-E drivers.
(pin 13) — Positive supply for TIA/EIA-232-E drivers.
, C1
, C2
(pin 11) — Power supply pin for the device,
±
10%).
−
−
(pins 12 and 14) — External capacitor connection
(pins 15 and 16) — External capacitor connection
CC
current to less than 10 µA. Pro-
FIGURE 6. Receiver TRI-STATE Timing (t
FIGURE 7. Receiver TRI-STATE Timing (t
5
(Continued)
D
TTL/CMOS compatible. Inputs of unused drivers may be left
open, an internal pull-up resistor (500 kΩ minimum, typically
5 MΩ) pulls input to V
D
form to TIA/EIA-232-E levels.
R
accept TIA/EIA-232-E input voltages (
ture a noise filter and guaranteed hysteresis of 200 mV.
Unused receiver input pins may be left open. Internal input
resistor (5 kΩ) pulls input LOW, providing a failsafe HIGH
output.
R
are TTL/CMOS compatible. Receiver output HIGH voltage is
specified for both CMOS and TTL load conditions.
GND (pin 10) — Ground pin.
IN
OUT
IN
OUT
1–5 (pins 9, 4, 27, 23 and 18) — Receiver input pins
1–4 (pins 7, 6, 20 and 21) — Driver input pins are
1–5 (pins 8, 5, 26, 22 and 19) — Receiver output pins
1–4 (pins 2, 3, 1 and 28) — Driver output pins con-
PHZ
PLZ
, t
, t
PZH
PZL
CC
)
)
01128109
01128110
. Output will be LOW for open inputs.
±
15V). Receivers fea-
www.national.com