AD8342ACPZ-WP Analog Devices Inc, AD8342ACPZ-WP Datasheet - Page 21

• Manufacturer Part Number: AD8342ACPZ-WP
• Manufacturer: Analog Devices Inc

Specifications of AD8342ACPZ-WP

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

EVALUATION BOARD
An evaluation board is available for the AD8342. The evaluation board is configured for single-ended signaling at the IF output port via a
balun transformer. The schematic for the evaluation board is presented in Figure 58. The representations of the board layout are included
in Figure 59 through Figure 62.
Table 7. Evaluation Board Configuration Options
Component
R1, R2, R7,
C2, C4, C5, C6, C9,
C10, C12, C13
R3, R4
R6, C11
R8
R9
C3, R5, C14, L1
C1
C8
C7
W1
T1, R10, R11, R12,
R15, R16, Z3, Z4,
Z1, Z2,
RF_IN
VPOS
PWDN
GND
OPEN
0Ω
L1
C14
0.1µF
0.1µF
Description
Supply decoupling. Shorts or power supply decoupling resistors and filter
capacitors.
Options for single-ended IF output circuit.
R
provides ac bypass for R6.
Pull down for the PWDN pin.
Link to PWDN pin.
RF input. C3 provides dc block for RF input. R5 provides a resistive input
termination. C16 and L1 are provided for reactive matching of the input.
RF common ac coupling. Provides dc block for RF input common
connection.
LO input ac coupling. Provides dc block for the LO input.
LO common ac coupling. Provides dc block for LO input common
connection.
Power down. The part is on when the PWDN is connected to ground via a
10 kΩ resistor. The part is disabled when PWDN is connected to the positive
supply (V
IF output interface. T1 converts a differential high impedance IF output to
single-ended. When loaded with 50 Ω, this balun presents a 100 Ω load to
the mixers collectors. The center tap of the primary is used to supply the
bias voltage (V
VPOS
BIAS
C2
C5
PWDN
resistor that sets the bias current for the mixer core. The capacitor
VPOS
0.1µF
R5
100Ω
C12
TRACE
W1
50Ω
0Ω
0Ω
R1
R2
S
) via W1.
S
R7
0Ω
C4
1000pF
C6
1000pF
) to the IF output pins.
1000pF
1000pF
C1
C3
C13
100pF
14
15
13
16
COMM
RFCM
RFIN
VPMX
VPDC PWDN EXRB COMM
VPLO LOCM LOIN COMM
1000pF
12
1
C7
R9
0Ω
11
2
10kΩ
DUT
Figure 58. Evaluation Board
R8
INLO
Rev. B | Page 21 of 24
10
3
C8
1000pF
COMM
COMM
1.82kΩ
9
4
IFOM
IFOP
R6
100pF
C11
8
7
6
5
OPEN
Z3
Z1
OPEN
R10
R11
R16
0Ω
0Ω
0Ω
OPEN
OPEN
R12
Z4
100pF
Z2
OPEN
C10
R15
0Ω
Default Conditions
R1, R2, R7 = 0 Ω
C4, C6 = 1000 pF
C10, C13 = 100 pF
C2, C5, C9, C12 = 0.1 μF
R3, R4 = Open
R6 = 1.82 kΩ
C11 = 100 pF
R8 = 10 kΩ
R9 = 0 Ω
C3 = 1000 pF
R5 = 100 Ω
C14 = Open
L1 = 0 Ω
C1 = 1000 pF
C7 = 1000 pF
T1 = TC2-1T, 2:1 (Mini-Circuits®)
R12 = Open
R10, R11, R15, R16 = 0 Ω
Z3, Z4 = Open
Z1, Z2 = Open
C8 = 1000 pF
R4
OPEN
TC2-1T
OPEN
3
2
1
R3
C9
0.1µF
T1
4
6
100Ω TRACES,
NO GROUND PLANE
VPOS
IF_OUT+
IF_OUT–
AD8342