TXC-03453BIOG Transwitch Corporation, TXC-03453BIOG Datasheet

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TXC-03453BIOG

Manufacturer Part Number
TXC-03453BIOG
Description
Manufacturer
Transwitch Corporation
Datasheet

Specifications of TXC-03453BIOG

Screening Level
Industrial
Package Type
BGA
Lead Free Status / Rohs Status
Not Compliant
U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096;
5,297,180; 5,289,507; 5,473,611; 5,535,218; 5,528,598; 6,463,111 B1
U.S. and/or foreign patents issued or pending
Copyright © 2003 TranSwitch Corporation
PHAST, TranSwitch and TXC are registered trademarks of TranSwitch Corporation
• Maps up to three independent DS3/E3 line formats into
• SDH/SONET bus access:
• Path overhead byte processing:
• Alarm indication port
• O-bit channel access via external interface
• Digital desynchronizer with internal pointer leak algorithm
• Line interface:
• Microprocessor access:
• Testing:
• A fully tested device driver is available
• 3.3 volt power supply, 5 volt tolerant inputs
• 324-lead plastic ball grid array package (23 mm x 23 mm)
FEATURES
SDH/SONET formats as follows:
- DS3 to/from STM-1/TUG-3
- DS3 to/from STS-3/STS-1
- E3 to/from STM-1/TUG-3
- Byte-wide drop and Add buses
- Drop bus timing mode (Add bus timing derived from
- Add bus timing mode (independent timing for
- Microprocessor access
- External interface
- B3 generation/detection with test mask
- B3 bit/block performance counters
- REI bit/block performance counters
- C2 mismatch detection
- C2 unequipped detection and generation
- Path REI count and RDI status for APS applications
- NRZ or P/N rail option for transmit and for receive
- Monitor NRZ transmit data
- Motorola or Intel compatible
- Hardware interrupt with mask bits
- Software polling bits
- Facility or line loopback
- PRBS generator/analyzer
- Boundary scan (IEEE 1149.1 standard)
Drop bus)
drop/Add buses)
SDH/SONET SIDE
(TELECOM BUS)
TranSwitch Corporation
Drop Bus
Add Bus
Tel: 203-929-8810
Interfaces
O-Bit
Microprocessor
3 Enterprise Drive
Interface
Triple Level 3 Mapper
Fax: 203-926-9453
Interfaces
External
Alarm
TXC-03453B
Indication
TL3M
Alarm
Port
DESCRIPTION
APPLICATIONS
Each of the three channels of the TL3M can map a DS3 line sig-
nal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET
signal. An E3 signal can be mapped only into an STM-1 TUG-3.
The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal
using a byte- wide parallel interface in the TranSwitch Telecom
Bus format. The TL3M supports Drop bus and Add bus SDH/
SONET timing modes. Drop bus timing provides the timing sig-
nals for the add side. Timing for both buses is independent for
the Add bus timing mode. Individual POH bytes are mapped into
a RAM interface for microprocessor access and to an external
interface for external processing if required. In the add direction
(except for the B3 byte) POH bytes may be inserted individually
from RAM locations, from the external interface, or from the local
side/alarm indication port. An option is provided to generate an
unequipped channel or AIS. An external interface is provided for
accessing the O-bits. An alarm indication port is provided for
ring operation. The TL3M also uses internal digital desynchro-
nizers that have a built-in pointer leak algorithm. The line side
can be configured for a NRZ or positive/negative rail interface.
For testing purposes, the TL3M provides boundary scan, PRBS
generators and analyzers, a BIP error mask, and DS3/E3 line
and facility loopbacks. The TL3M provides either Motorola or
Intel microprocessor access. The interrupt has programmable
mask bits. A software polling register is also provided.
• Add/drop multiplexers
• Add/drop multiplexers
• Digital cross connect systems
• Digital cross connect systems
• Broadband switching systems
• Broadband switching systems
• Transmission equipment
• Transmission equipment
Control
Signals
Shelton, Connecticut 06484
Boundary
Scan
www.transwitch.com
Interfaces
POH
PRELIMINARY TXC-03453B-MB, Ed. 3
Triple Level 3 Mapper
Transmit Interfaces (3)
Receive Interfaces (3)
LINE SIDE
Transmit Monitor
Interfaces (3)
(Rail, NRZ)
(Rail, NRZ)
TL3M Device
DATA SHEET
Document Number:
TXC-03453B
USA
September 2003

Related parts for TXC-03453BIOG

TXC-03453BIOG Summary of contents

Page 1

... U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096; 5,297,180; 5,289,507; 5,473,611; 5,535,218; 5,528,598; 6,463,111 B1 U.S. and/or foreign patents issued or pending Copyright © 2003 TranSwitch Corporation PHAST, TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DESCRIPTION Each of the three channels of the TL3M can map a DS3 line sig- nal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal ...

Page 2

... They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET TABLE OF CONTENTS ...

Page 3

... Proprietary TranSwitch Corporation Information for use Solely by its Customers Figure 1. Typical Application using the TL3M and PHAST-3N Devices ........................................... 8 2. TL3M TXC-03453B Block Diagram ................................................................................... 9 3. TL3M Multiplexing Structure ............................................................................................ 10 4. SONET AU-3/STS-1 SPE Build Format .......................................................................... 12 5. ITU-T TUG-3 Build Format .............................................................................................. 13 6. TL3M TXC-03453B Lead Diagram .................................................................................. 15 7 ...

Page 4

... The TL3M provides the following additional bus features: • SDH/SONET interface Drop bus • Input parity check with alarm monitoring • Odd parity • Bus signals • Input loss of clock detection • Stuck high or low • Loss of J1 reference PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET - ...

Page 5

... Signal label mismatch and unequipped detection • POH byte Insertion (TUG-3, STS-1) • All POH bytes • Microprocessor access • POH interface • Control bits to determine source of input bytes • J1 byte • 64-byte message DATA SHEET - PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B September 2003 ...

Page 6

... Clock, positive and negative rail signals • DS3/E3 loss of signal detection in transmit direction • BPV counter • DS3 B3ZS or E3 HDB3 codec function • Loss of clock detector • Invert clock polarity (receive and transmit) PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET - ...

Page 7

... Hardware interrupt option • Mask bits • Positive level • Software polling bit • Latched and unlatched alarms • Saturating or rollover counters option Device Driver: • Device configuration • Fault monitoring • Performance monitoring DATA SHEET - PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B September 2003 ...

Page 8

... DS3’s may be dropped from either direction with full time slot reuse in both directions. If required, the asynchro- nous line interfaces for the two TL3M devices may be tied together. An option is provided in which the output line interface can be forced to the high impedance state. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 9

... RnOCC O-BIT RnOCD INTERFACE TnOCC BLOCK TnOCD ACLK AC1J1 BUILD ADD ASPE BLOCK BLOCK ADD AD(7-0) APAR Figure 2. TL3M TXC-03453B Block Diagram DATA SHEET Note channels RECEIVE DESTUFF DESYNC BLOCK BLOCK GENERATION TRANSMIT STUFF/ SYNC BLOCK PROCESSOR INTERFACE INTERNAL RAM BLOCK ...

Page 10

... ETSI and ANSI documents. Performance counters are provided for justification events. The TL3M does not perform pointer tracking for the STS-1 signals, or for the VC-4 formats. Instead, the J1 indication is used as the start of format indication. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 11

... The rail interface also detects DS3 loss of signal. The input clock is also monitored for a stuck high or low condition. When the NRZ interface is selected, the unused negative rail input lead can be used to clock in an external loss of signal (LOS) indication from a downstream codec. DATA SHEET - PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B September 2003 ...

Page 12

... C1J1. The pointer movement for the TUG-3s will be in the opposite direction. This feature can be disabled. POH 8R 8R RRC 5I 200I 8R 8R CCRRRRRR 208I 8R 8R CCRROORS Figure 4. SONET AU-3/STS-1 SPE Build Format PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET DS3 44.736 Mbit/s Subframe Format ( ...

Page 13

... Note: Normally the two O-bits in the E3 format are designated as Reserved TUG-3 Format ( Figure 5. ITU-T TUG-3 Build Format 208I 8R CCRROORS RRRROOC1C2 24I C C 24I RRRROORR RRRRRRRS1 S2IIIIIII 24I 24I 24I 24I 24I C 24I 24I 24I 24I 24I PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B 208I 85 85 September 2003 ...

Page 14

... For board testing, boundary scan and the ability to force all the output signals to a high impedance state are provided. For network and device debugging, facility and line loopbacks are provided at the line interfaces. Each channel also has a PRBS test analyzer and generator (not shown in Figure 2). PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 15

... This is the bottom view. The leads are solder balls. See Figure This view is rotated relative to the bottom view in Figure 2. Lead symbols are described in the “Lead Descriptions” section. 3. Power supply leads are shown as solid black circles, ground leads as cross-hatched circles. Figure 6. TL3M TXC-03453B Lead Diagram DATA SHEET BOTTOM VIEW RD ...

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... C4, C19, C21, D5, D6, D9, D10, D13, D14, D17, D20, D22, E4, E19, F4, J4, K4, N4, P3, R2, R3, T3, U2, U4, U19, V4, V19, W5, W14, W17, W18, Y14, Y15 * Note Input Output Power Tristate: PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET I/O/P* Name/Function P Core VDD: +3.3 volts, 5% power supply VDD: +3 ...

Page 17

... Drop bus timing mode is selected (lead ABTIM is low). I LVTTL Drop Bus Parity Bit: Odd parity input for the data byte, the DSPE signal, and the composite DC1J1 pulse. section for Type definitions TL3M TXC-03453B Name/Function PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 18

... ACLK P1 ASPE N3 AC1J1 N2 ADD P2 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Type LVCMOS Add Bus Data Byte: 19.44 Mbytes/s byte-wide data that 4mA corresponds to the time slots that are placed on the Add bus by the TL3M. Lead K1 is AD7. The first bit transmit- ted (MSB) corresponds to bit 7 ...

Page 19

... Control bit L3OEN (bit 0 in XC2H) is set to 0 for the corresponding channel - Hardware reset (lead RESET) or software reset (RESETS, bit 0 in 0C7H) occurs - RESETn (bits 1-3 in 0C7H) is set to 1 for the corre- sponding channel TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 20

... AB19 R1NRD E21 O (T) R2NRD G22 R3NRD AA20 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Type LVCMOS Receive Line Clock for Channel n: The 44.736 or 4mA 34.368 Mbit/s line signals on the RPOSn/RNEGn signal leads are clocked out on falling edges of this clock when control bit INVCO (bit 4 in XC1H) is set to 0 for the corre- sponding channel ...

Page 21

... Transmit Overhead Communications Channel Clock: 4mA A gapped 720 kHz output clock that has an average fre- quency of 144 kHz, which is used for clocking in the transmit overhead communications channel bits (TnOCD) from external circuitry when enabled TL3M TXC-03453B Name/Function Name/Function PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 22

... A17 T3POF B20 T1POC B13 T2POC B16 T3POC C18 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Type O LVCMOS Receive Path Overhead Byte Data: These leads pro- 4mA vide a serial output for the nine path overhead bytes associated with each of the three TUG-3s or STS-1s. ...

Page 23

... Transmit Alarm Indication Port Framing Pulse: Nor- mally connected to receive path overhead byte framing pulse output leads (RnPOF) at the mate TL3M device for a ring configuration. Used to indicate the location of the first bit in the byte TL3M TXC-03453B Name/Function RDI PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 24

... ISTA1 AB14 ISTA2 AB15 ISTA3 AB16 TRI AB17 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Type I LVTTL DS3 AIS Clock Input: Input clock for the DS3 AIS gener- ator. This clock must be present for the DS3 AIS genera- tor to function. The clock must have the operating line rate of 44.736 MHz, and a frequency stability of ± ...

Page 25

... The indication will be high for a minimum of 125 microseconds and a maximum of 250 microseconds for any of the following - Hardware Reset (RESET lead goes low) - RESET (bit 0 in 0C7H RESETn (0C7H) is set to 1 for the corresponding channel. - FIFO overflow or underflow - TL3M TXC-03453B Name/Function PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 26

... AB5, Y3, Y6, AA5, AB4 AB7 or RD/WR SEL AA7 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Type I Analog Transmit Synthesizer Bias Components: An external 30 resistor is connected between the GRS1 lead and the SBS1 lead. A 220 pF bypass capacitor is connected between the SBS1 node and ground, as shown in the Synthesizer connections diagram (Figure 28) ...

Page 27

... Motorola microprocessor compatible bus interface. A low selects the Intel microprocessor compatible bus inter- face TL3M TXC-03453B Interrupt Lead 0 High impedance state 1 Interrupt lead held to the high-z state only when inactive 1 Interrupt lead enabled for normal operation PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 28

... TSCKT C14 SUB AB2 ADD Y4 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Type LVCMOS Boundary Scan Test Data Output: Serial data clocked 4mA out on falling edges of TCK. I LVTTLp Boundary Scan Test Data Input: Serial data input for boundary scan test messages. ...

Page 29

... TL3M TXC-03453B Unit Conditions V Note 1 V Note Note ft/min linear airflow Level per EIA/JEDEC JESD22-A112-A % Note 2 % non-condensing V Note 3 Unit Test Conditions o C/W 0 ft/min linear airflow Unit Test Conditions max VDD, -40 to +85 (see Note 1) PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 C ...

Page 30

... Input capacitance OUTPUT PARAMETERS FOR LVCMOS 4mA Parameter Min 4 Leakage Tristate -10 Output Capacitance t RISE t FALL PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Typ Max 0.8 +10 5.0 Typ Max 0.8 0.0 5.0 Typ Max 0.8 100 5.0 Typ Max - 0.5 0.4 -4.0 +10 7 ...

Page 31

... Typ Max 0.8 +10 7.0 0.4 -8 TL3M TXC-03453B Unit Test Conditions 3.15 -8 3.15 8 5.25 V input 25pF LOAD 25pF LOAD Unit Test Conditions V 3. 3. 5.25 V input 3.15 -8 3.15 8 25pF LOAD 25pF LOAD PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 32

... TCLKn duty cycle PWH(1) CYC(1) TPOSn/TNEGn setup time before TCLKn TPOSn/TNEGn hold time after TCLKn RnNRC clock period RnNRC duty cycle PWH(2) CYC(2) RnNRD output delay after RnNRC Note 1: 22.35 ns (DS3) or 29.10 ns (E3). PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET + CYC(1) t PWH( ...

Page 33

... RCLKn clock period RCLKn duty cycle PWH CYC RPOSn/RNEGn data output delay after RCLKn Note 1. 22.35 ns (DS3) or 29.10 ns (E3). DATA SHEET t CYC t PWH Symbol Min Typ t See Note 1 CYC --- 0 PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B NRZ Interface Rail Interface Max Unit 2.0 ns September 2003 ...

Page 34

... Facility loopback is enabled when control bit FLBK (bit 2 in XC1H) is set to 1. Parameter RCLKn clock period RCLKn duty cycle PWH CYC RPOSn/RNEGn data output delay after RCLKn edge (same relation as on TCLKn to TPOSn/ TNEGn in facility loopback). Note 1: 22.35 ns (DS3) or 29.10 ns (E3). PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET t CYC t PWH ...

Page 35

... Symbol Min t CYC -- 40 t 1.0 SU(1) t 4.0 H(1) t 1.0 SU(2) t 4.0 H(2) t 5.0 OD(1) t 7.0 OD(2) t 6.0 OD(3) t 5.0 OD( TL3M TXC-03453B t OD(3) STUFF H1 BYTE TUG-3 FOR J1 t OD(2) t OD(4) Typ Max Unit 51. 12.0 ns 13.0 ns 14.0 ns 12.0 ns PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 36

... ASPE setup time before ACLK ASPE hold time after ACLK AD(7-0) and APAR output delay from ACLK ADD low output delay from ACLK AD(7-0) and APAR tristate delay from ACLK ADD high output delay from ACLK PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET t CYC t ...

Page 37

... PWH CYC DD(7-0) data/DPAR/DC1J1/DC1/DSPE setup time before DCLK DD(7-0) data/DPAR/DC1J1/DC1/DSPE hold time after DCLK DATA SHEET t CYC t PWH C1( Symbol Min t CYC -- TL3M TXC-03453B FIXED FIXED H1(1) H1(2) STUFF STUFF TUG-3 TUG-3 Typ Max Unit 51. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 38

... C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded. Parameter DCLK clock period DCLK duty cycle PWH CYC DD(7-0) data/DPAR/DC1J1/DC1/DSPE setup time before DCLK DD(7-0) data/DPAR/DC1J1/DC1/DSPE hold time after DCLK PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET t CYC t PWH ...

Page 39

... H(1) t 1.0 SU(2) t 4.0 H(2) t 5.0 OD(1) t 7.0 OD(2) t 6.0 OD(3) t 5.0 OD( TL3M TXC-03453B H1(2) H1(1) FIXED FIXED STUFF TUG-3 STUFF TUG-3 t OD(1) FIXED STUFF FOR J1 t OD(3) t OD(4) Typ Max Unit 51. 15.0 ns 15.0 ns 15.0 ns 12.0 ns PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 40

... DSPE setup time before DCLK DSPE hold time after DCLK AD(7-0) data and APAR delay after DCLK ADD indicator delayed after DCLK AD(7-0) data and APAR tristate after DCLK ADD indicator high after DCLK PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET t CYC t ...

Page 41

... TnPOF pulse width DATA SHEET Bit 3 J1 Bit 4 J1 Bit 5 J1 Bit 6 J1 Symbol Min t 617 PWH t PWL TL3M TXC-03453B t PWH Bit 7 J1 Bit 8 J1 Bit 1 B3 Typ Max Unit 3395 ns 772 ns 2 1389 ns PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 42

... Note: The clock cycle that corresponds to bit 8 in each overhead byte is stretched. Parameter RnPOC low time RnPOC high time RnPOF output delay after RnPOC RnPOD output delay after RnPOC RnPOF pulse width PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Bit 3 J1 Bit 4 J1 Bit 5 J1 Bit 6 J1 ...

Page 43

... DATA SHEET t H(1) Bit 3 Bit 4 Bit 5 Bit 6 Byte 1 Byte 1 Byte 1 Byte 1 Symbol Min t 617 PWL t PWH t 2.0 SU(1) t 1.0 H(1) t 2.0 SU(2) t 1.0 H( TL3M TXC-03453B t PWL Bit 7 Bit 8 Bit 1 Byte 1 Byte 1 Byte 2 Typ Max Unit 3395 ns 772 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 44

... Parameter RnPOC low time RnPOC high time RnPOF output delay after RnPOC RnAID output delay after RnPOC RnPOF pulse width PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Bit 3 Byte 1 Bit 4 Byte 1 Bit 5 Byte 1 Bit 6 Byte 1 ...

Page 45

... RnOCC low time RnOCD output delay after RnOCC DATA SHEET t PWL Symbol Min t PWH t 617 PWL PWL t PWH Symbol Min t PWH t 4646 PWL t 0 TL3M TXC-03453B Typ Max Unit 772 ns 11900 Typ Max Unit 772 ns 7700 ns 3.5 ns PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 46

... Note 1: RDY goes low when the address being read corresponds to a RAM location but remains high during status or control register access the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25MHz yields CYC t = 1.92 s max). PW(2) PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET t D(1) t SU(2) t ...

Page 47

... SU(2) t SU(4) t SU(3) t PW( D(1) D(2) t PW(2) Symbol Min Typ t 4.0 H(1) t 0.0 SU(1) t 4.0 SU(2) t 3.0 H(2) t 10.0 SU(3) t 40.0 PW(1) t D(1) t D(2) t 0.0 PW( Rcyc SU( TL3M TXC-03453B t H( Max Unit 16 Rcyc ns 13 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 48

... RD/WR hold time after SEL DTACK delay after SEL DTACK pulse width (See Note 1) DTACK float time after SEL Note the period, in nanoseconds, of the RAM clock (RAMCI). CYC (e.g., RAMCI @ 25 MHz yields t PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET t PW(1) t SU(2) t ...

Page 49

... SU(1) t SU(3) t PW( Symbol Min t 5.0 H(1) t 2.0 SU(1) t 6.5 SU(2) t 5.0 H(2) t 40.0 PW(1) t 5.0 SU(3) t 5.0 H( 0.0 PW( Rcyc SU(4) = -80 ns min 1.92 s max). SU(4) PW( TL3M TXC-03453B t H(1) t H( Typ Max Unit 15 Rcyc ns 11 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 50

... TMS setup time before TCK TMS hold time after TCK TDI setup time before TCK TDI hold time after TCK TDO output delay after TCK TRS pulse width PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Figure 26. Boundary Scan Timing PWH t H(1) ...

Page 51

... Alternate: 4.7 F, 6.3V ceramic X5R 1206. Traces should be kept as short as possible. Place the external components as close as possible to the associ- ated device leads. Please refer to AN-537 (TXC-03453-AN1) for additional recommendations for board layout design. This Application Note is available on the TL3M page of the TranSwitch web site, www.transwitch.com. ...

Page 52

... W&G ANT20 Min interval = 15mS 3: Valid for DS3 mapped up to +/-45ppm 4: Data errors never occurred during the tests low jitter COMBUS reference clock is required 5: Jitter measured with standard filters: HP=10 Hz, LP=400 kHz PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Maximum Jitter Limit Specified by ...

Page 53

... ETSI EN 300 417-1-1 V1.1.3 (UIpp) at RCLKn output HP1/LP HP2/LP HP1/LP 0.063 0.045 0.4 0.063 0.054 0.4 0.078 0.050 0.4 0.099 0.050 0.4 0.059 0.044 0. PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B ITU-T G.783 (UIpp) See Note 2 HP2/LP 0.075 0.075 0.075 0.075 0.075 September 2003 ...

Page 54

... T=1S (GR-253-CORE Fig. 5-42). Note 1: Minimum observation is 1 Sec. since sample rate was set to 1 Sec. General measurement note: Min. MTIE interval is 0.1 Sec., Max 100 Sec. per GR-253-CORE PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Observation Time, S 0.1 Sec. ...

Page 55

... General measurement note: Min. MTIE interval is 0.1 Sec., Max 100 Sec. per GR-253-CORE Figure 31. STS-1 Pointer Movements on DS3 Payload DATA SHEET Observation Time, S 0.1 Sec. 1.0 Sec. MTIE Limit MTIE Limit (nS) (nS) (nS) (nS) 11 183 22 800 - TL3M TXC-03453B 10 Sec. 100 Sec. MTIE Limit MTIE Limit (nS) (nS) (nS) (nS) 25 800 90 800 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 56

... Note: At frequencies above 30 KHz, the TL3M exceeds the Jitter Transfer Mask because the applied jitter is attenuated below the generated jitter level. The generated jitter is well within the specification. This result is consistent with limi- tations of the test equipment and open-ended nature of the specification (-20dB slope with no plateau). PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 57

... Proprietary TranSwitch Corporation Information for use Solely by its Customers DATA SHEET Figure 34. Jitter Tolerance for E3 (ITU G.751 Fig. 2) Figure 35. Jitter Transfer for E3 (from ITU G.823 Fig. 15 PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B September 2003 ...

Page 58

... TXANA, the transmit NRZ data path is monitored. The selection of the test analyzer disables the decoder cod- ing violation count to the 16-bit CV counter in registers XAEH and XAFH. Instead, this 16-bit counter is config- ured to count PRBS test analyzer errors when in lock. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 59

... Errors PRBS 0 Analyzer ENANA RPBRS 1 HDB3 B3ZS 1 Coder DAISC, DS3/E3 EAISC AIS GEN FLBK - TL3M TXC-03453B L3LBK Line In 0 (TX DS3/E3) 1 Counter L3LBK & LLBAIS FLBK Output L3LBK & LLBAIS Rx Output Data 0 1 DS3/E3 AIS Data Data PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 60

... There are 163 scan cells in the TL3M boundary scan chain. Bidirectional signals require two scan cells. Addi- tional scan cells are used for direction control as needed. A Boundary Scan Description Language (BSDL) source file is available via the Products page of the TranSwitch World Wide Web site (www.transwitch.com). PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 61

... DEVICE MEMBIST Register ID Register Instruction Register Bypass Register TAP Controller 3 TDI Clock, Controls TCK, TMS, TRS IN Boundary Scan Serial Test Data TDO OUT - PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B Signal input and output leads (solder balls on bottom surface of PBGA package) September 2003 ...

Page 62

... The part number of the TL3M is 03453, which is expressed as a binary number in bits 3 through 0 in register 0F3H, bits 7 through 0 in register 0F2H, and bits 7 through 4 in register 0F1H. The revision field is in bits 7 through 4 of register 0F3H. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET ...

Page 63

... TSTCH1 TSTCH0 LLBAIS RESET2 RESET1 RESETS Bit 3 Bit 2 Bit 1 Bit 0 APOS0 Reserved DS3 RING FLBK L3LBK Reserved Reserved ADBEN L3OEN EXF2 EXG1 EXC2 EXJ1 RAISEN WGDEC PSL2AIS TXANA TPRBS RPRBS TXRST RXRST RESETC RDI5 REIBLK Reserved PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 64

... Address Mode Bit 7 (Hex) XBA R/W DLOC XBB R/W RDI XBC R/W HINT Reserved XBD R/W L3ERR PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Reserved Reserved Not Used Reserved Reserved Bit 6 Bit 5 Bit 4 Reserved Not Used Not Used ...

Page 65

... Receive B3 Byte Receive C2 Byte Receive G1 Byte Receive F2 Byte Receive H4 Byte Receive F3 Byte Receive K3 Byte Receive N1 Byte Receive TUG-3 H1 Byte Receive TUG-3 H2 Byte Not Used - TL3M TXC-03453B Bit 2 Bit 1 Bit 0 TOBIT2 TOBIT1 Bit 2 Bit 1 Bit 0 ROBIT2 ROBIT1 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 66

... XAC R XAD R XAE R XAF R XFF R Common High Order Byte Counter Snapshot (REI, B3, Coding Violations) PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 Receive SDH/SONET Frame Counter (8 bits) Reserved FIFO Leak Rate Register (8 bits) Positive Justification (Increment) Counter (8 bits) ...

Page 67

... RNEGn (Receive Negative Rail) - RnNRD (Transmit Monitor NRZ Data) - RnNRC (Transmit Monitor NRZ Clock forces these signals to a high impedance state, regardless of the state of L3OEN. A hardware or software reset forces this bit to the 0 state. Reserved Reserved - TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 68

... RESET2 1 RESET1 0 RESETS PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description Reserved: Must be set to zero when register is written. TranSwitch Test Control Bits: These bits are used for selecting test con- ditions for each of the three channels. These bits must be set to 00 for nor- mal operation ...

Page 69

... TUG-3 position C (or STS-1 # not use Reserved: Must be set to zero when register is written. DS3 Mode: Determines the line to SDH/SONET mapping mode according to the table given below: DS3 Mapping Mode 0 E3 (34.368 Mbit/s) 1 DS3 (44.736 Mbit/ TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 70

... CODE 5 INVCI 4 INVCO PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description Transmit Line Decoder Enabled enables the transmit HDB3/ B3ZS decoder (for rail operation disables the decoder (for NRZ operation). This control bit also selects the transmit line interface to be either positive/ negative rail (decoder enabled) or NRZ ...

Page 71

... E1AIS (Alarm) XALM2AIS=0 ISTAn lead high + & PAISn lead high XALM2AIS=1 + PSLERR (Alarm) C2EQ0 (Alarm) PSL2AIS=1 A SDH/SONET Channel n BUS D A SDH/SONET Channel n BUS TL3M TXC-03453B & Send RDI + for Channel n & TX DS3/ DS3/E3 RX DS3/E3 AIS OPTION PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 72

... TPAISGN 3 TPAIS00 2 1 ADBEN PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description External Alarm Enable AIS enables an AIS detected in the SDH/ SONET E1 byte (when control bit XALM2AIS = high on either the ISTAn or PAISn leads (when control bit XALM2AIS = 1) to generate DS3 or E3 line AIS in the receive direction when control bit RAISEN See logic diagram for Address XC5H, bit 2 ...

Page 73

... Transmit External Interface J1 Bytes enables the J1 bytes from the POH input/output interface to be transmitted enables the correspond- ing RAM segment (64 locations transmitted. DATA SHEET Description L3OEN 0 0 All receive channels high All receive channels high Per channel high Receive outputs enabled - TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 74

... XC4 7 EXOO 6 5 RAMRDI PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description External O-Bit Select selects the two Overhead Communication Bits (O-bits) from the external interface (lead TnOCD) as the two O-bits trans- mitted in each of the nine subframes of the DS3 format or TranSwitch des- ignated reserved bits in each of the three subframes of the E3 format ...

Page 75

... RING=0 AIP REI count & RING=1 REIEN=1 REIEN=0 & RAM REI Value EXG1=0 L3LOC (Alarm) & TLOC2AIS=1 + L3LOS (Alarm) & TLOS2AIS=1 TLAISGN TL3M TXC-03453B & + & + SEND REI for Channel n SEND DS3 or E3 AIS for Channel n PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

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... POH2RAM Path Overhead Bytes to RAM: This bit works in conjunction with the (cont.) 3 RAISGN 2 RAISEN PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description EXnn control bits that select POH bytes (e.g., EXF2). The following table summarizes the action taken by this bit and an EXnn bit: POH2RAM EXnn (reg ...

Page 77

... B000V after even 10000 23 -1 Test Pattern Enable selects the two PRBS test pattern genera TL3M TXC-03453B “Type 0” Equipment 11 011 or 0001 1101 1001 “Type 0” Equipment 11 011 or 00001 11001 10001 15 - selects the pat analyzer. PRBS errors PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 78

... REIBLK XCA 7-6 5 NOPOH 4-0 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description TUG-3 Fixed Pointer Generation forces a fixed pointer generated in the transmitted TUG-3 regardless of any pointer movements (J1 in DC1J1) that may occur on the Drop side when the Drop timing mode is selected pointer movement (J1 in AC1J1) takes place when Add bus timing is selected ...

Page 79

... Recovery occurs when the J1 pulse is detected in the same location for 8 consecutive frames. DATA SHEET Description Description - 8 consecutive new J1 positions have been detected stuck low for 8 consecutive frames stuck high for 8 consecutive bytes pulses are received in one frame TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 80

... RDI 6 L3LOS 5 L3LOC PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description Bus Parity Error: This unlatched alarm indicates that a parity error has been detected on the Drop bus. Odd parity is calculated over the DD(7-0), DSPE, DC1J1, and DC1 leads. Other than providing this alarm, no action is taken by the channel or device ...

Page 81

... FIFO will automatically reset to a preset position and the FIFO Reset Indi- cation output lead (DFnE) will pulse high. DATA SHEET Description - 8 consecutive new J1 positions have been detected stuck low for 8 consecutive frames stuck high for 8 consecutive bytes pulses are received in one frame TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 82

... RPLOC 0 OOL XB7 7-0 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description AIS Loss Of Clock Detected: The AIS selected (DS3 or E3) is monitored for a stuck high or stuck low condition, An unlatched AIS LOC indication occurs when the EAIS or DAIS clock is stuck high or low for approximately 225 ns ...

Page 83

... C2 Equal to 0 alarm (unequipped) Receive RDI (yellow) detected. Transmit Line Loss Of Signal Transmit Line Loss Of Clock Transmit FIFO Error (underflowed or overflowed) E3 Transmit Line AIS Detected RAM Loss Of Clock Add Bus Loss Of Clock Add Bus Loss TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 84

... XC5H, bit 4 XC3H, bits 7 e.g C2. PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description Hardware Interrupt Enable Reserved: Must be set to zero when register is written. New Alarm - NDF and 3x new pointer events (TUG-3 operation) Receive FIFO Overflow/Underflow Alarm Indication Signal Loss Of Clock External STS-1 Alarm (ISTAn) signal detected (if enabled) External Path AIS (PAISn) signal detected (if enabled) Internal PRBS Test Analyzer bit error detected ...

Page 85

... When control bit TESTB3 the value written into this register location is the transmitted B3 byte. Transmit Path Signal Label (microprocessor-written value): The bits of the C2 byte that are written into this position indicate the construction of the AU-3, TUG-3, or SPE (e.g., unequipped TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 86

... N1 X48 7-0 X49 7-2 1 TOBIT2 0 TOBIT1 PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description Transmit G1 Byte: This byte is used for sending the microprocessor-controlled states for REI, RDI, and any unassigned bits, according to the states given in the tables below: TFEBE EXG1 REIEN ...

Page 87

... Receive O-Bits: The received states of the two Overhead Communication channel bits found in the nine subframes in the DS3 format or the three TranSwitch-designated subframes in the E3 format. The two bits are updated once a frame from one of the subframes in the frame TL3M TXC-03453B (X99H PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 88

... Cnt XA1 7-0 XA2 7-0 FIFO Leak Rate PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Description Receive SDH/SONET Frame Counter: Counts the number of received SDH/SONET frames. This register is not cleared by a software reset and must be written to 00H to be cleared. Reserved FIFO Leak Rate Register: When a value greater then 00H is written into this location, this number represents the number of frames between con- secutive leaked bits, in multiples of four frames (i ...

Page 89

... XFFH. Common High Order Byte Counter Snapshot: This location contains a copy of the high order byte value that existed when the low order byte of a 16-bit counter was last read (i.e., registers XABH, XADH, or XAFH TL3M TXC-03453B PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 ...

Page 90

... TL3M TXC-03453B PACKAGE INFORMATION The TL3M device is packaged in a 324-lead plastic ball grid array package suitable for surface mounting, as illustrated in Figure 38 TRANSWITCH TXC-03453BIOG Note E1/4 D1/4 A2 (A3) Notes: 1. All dimensions are in millimeters. Values shown are for refer- ence only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90° ...

Page 91

... Proprietary TranSwitch Corporation Information for use Solely by its Customers ORDERING INFORMATION Part Number: TXC-03453BIOG RELATED PRODUCTS TXC-02030, DART VLSI Device (Advanced E3/DS3 Receiver/Transmitter). DART performs the transmit and receive line interface functions required for transmission of E3 (34.368 Mbit/s) and DS3 (44.736 Mbit/s) signals across a coaxial interface. ...

Page 92

... Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia-Antipolis Cedex, France PRELIMINARY TXC-03453B-MB, Ed. 3 September 2003 DATA SHEET Tel: (212) 642-4900 Fax: (212) 398-0023 Web: www.ansi.org Tel: (415) 561-6275 Fax: (415) 561-6120 Web: www ...

Page 93

... Tel: (800) 433-5177 (within U.S.A.) Tel: (503) 291-2569 (outside U.S.A.) Fax: (503) 297-1090 Web: www.pcisig.com Tel: (800) 521-2673 (within U.S.A.) Tel: (732) 699-2000 (outside U.S.A.) Fax: (732) 336-2559 Web: www.telcordia.com Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or. PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B September 2003 ...

Page 94

... Updated TL3M TXC-03453B Data Sheet: PRELIMINARY Edition 3, September 2003. Previous TL3M TXC-03453B Data Sheet: PRELIMINARY Edition 2, June 2002. The page numbers indicated below of this updated TXC-03453B Edition 3 Data Sheet include significant changes relative to the previous TXC-03453B Edition 2 Data Sheet. Page Number of ...

Page 95

... PRELIMINARY information documents contain information on products in the sampling, pre-production or early pro- duction phases of the product life cycle. Characteristic data and other specifications are subject to change. Contact TranSwitch Applications Engineering for current information on this product PRELIMINARY TXC-03453B-MB, Ed. 3 TL3M TXC-03453B September 2003 ...

Page 96

... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 • • Fax: 203-926-9453 www.transwitch.com ...

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