TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet
TXC-04251AIPQ
Specifications of TXC-04251AIPQ
Related parts for TXC-04251AIPQ
TXC-04251AIPQ Summary of contents
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... Boundary U.S. Patents No.: 4,967,405; 5,033,064; 5,040,170; 5,265,096; 5,289,057 U.S. and/or foreign patents issued or pending Copyright 2000 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation TranSwitch Corporation Tel: 203-929-8810 DESCRIPTION The Quad T1 Mapper device is designed for add/drop multiplexer, terminal multiplexer, and dual and single uni- directional ring applications ...
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... They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. TXC-04251-MB Ed. 4, March 2000 DATA SHEET TABLE OF CONTENTS ...
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... Boundary Scan Timing ........................................................................................................ 28 13. H4 Byte Floating VT Mode Bit Allocation ............................................................................. 34 14. VT/TU Pointer Tracking State Machine ............................................................................... 41 15. Facility and Line Loopbacks ................................................................................................ 47 16. Boundary Scan Schematic .................................................................................................. 50 17. QT1M TXC-04251 160-Pin Plastic Quad Flat Package ....................................................... 86 DATA SHEET LIST OF FIGURES - 3 - QT1M TXC-04251 Page TXC-04251-MB Ed. 4, March 2000 ...
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... QT1M TXC-04251 This page has been intentionally left blank. TXC-04251-MB Ed. 4, March 2000 DATA SHEET - 4 - ...
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... Scan I/O TDO TRS Figure 1. QT1M TXC-04251 Block Diagram BLOCK DIAGRAM DESCRIPTION The block diagram for the Quad T1 Mapper is shown in Figure 1. The Quad T1 Mapper interfaces to four buses, designated as A Drop, B Drop, A Add, and B Add. The four buses run at the STS-3/STM-1 rate of 19.44 Mbyte/ the STS-1 rate of 6 ...
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... T1 loop buffer. The pointer leak buffer can accept up to five consecutive pointer movements, and can adjust the effect over time. The T1 Loop Buffer consists of a digital loop filter, which is designed to track the fre- quency of the received T1 signal and to remove both transmission and stuffing jitter. TXC-04251-MB Ed. 4, March 2000 DATA SHEET ...
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... The Boundary Scan Interface block provide a five-pin Test Access Port (TAP) that conforms to the IEEE 1149.1 standard. This standard provides external boundary scan functions to read and write the external I/O pins from the TAP for board and component test. DATA SHEET - 7 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... Negative Justification = Invert five D-bits Pointer Range = 0 - 103 decimal BIP-2 = Bit Interleaved Parity (2 bits) FEBE = Far End Block Error Indication RFI = Remote Failure Indication Signal Label RDI = Remote Defect Indication TXC-04251-MB Ed. 4, March 2000 DATA SHEET bytes (1.544 Mbit/s Data bytes (1 ...
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... TEST SEL RD WR ALE 150 INTSH GND INT/INT Reserved VDD 155 RESET Reserved ABUST Reserved Reserved Reserved Figure 3. QT1M TXC-04251 Pin Diagram DATA SHEET QT1M Pin Diagram (Top View) TXC-04251 - 9 - QT1M TXC-04251 80 NC VDD BADD BAPAR BA7 75 BA6 GND BA5 ...
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... Pin No. I/O/P ADCLK 26 I ADPAR See Input, Output and Input/Output Parameters section for Type definitions. TXC-04251-MB Ed. 4, March 2000 DATA SHEET I/O/P * Type VDD: +5 volt supply voltage, ±5 Ground: 0 volt reference. No Connect: NC pins are not to be connected, not even to another NC pin, but must be left floating. NC ...
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... A Add Bus SPE Indicator: When the add bus timing mode is selected, this signal must be provided for add bus timing. This signal must be high during each byte of the STS-3/STM-1/STS-1 payload, and low during Transport Overhead byte times QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... BDPAR 91 I BD(7-0) 90, 89, I 88, 87, 85, 84, 83, 82 TXC-04251-MB Ed. 4, March 2000 DATA SHEET Type * Name/Function TTL A Add Bus C1J1V1 Indications: When the add bus timing mode is selected, this signal must be provided for add bus timing. An active high timing signal that carries STS-3/STM-1/STS-1 starting frame and SPE information ...
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... B Add Bus SPE Indicator: When the add bus timing mode is selected, this signal must be provided for add bus timing. This signal must be high during each byte of the STS-3/STM-1/STS-1 payload, and low during Transport Overhead byte times QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... I (n=1-4) 6, 118 TPIn 21, 104, I (n=1-4) 8, 116 TXC-04251-MB Ed. 4, March 2000 DATA SHEET Type Name/Function TTL B Add Bus C1J1V1 Indications: When the add bus timing mode is selected, this signal must be provided for add bus timing. An active high timing signal that carries STS-3/STM-1/STS-1 starting frame and SPE information ...
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... INTSH pin. TTL Interrupt Sense High Selection: A high on this pin causes the interrupt sense to be high when an interrupt occurs. A low causes the interrupt sense to be low when an interrupt occurs QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... I TDI 38 I TDO 37 O TRS 35 I TXC-04251-MB Ed. 4, March 2000 DATA SHEET Type Name/Function TTLs TranSwitch Test Bit: A high must be placed on this pin. CMOS External Reference Clock: This clock is used for desynchronizer operation and other purposes. The clock frequency must be 48.6360 MHz (+/- 32 ppm over life) and the clock duty cycle must be 50 +/- 10% ...
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... Note 2 V Note 3 Unit Test Conditions o C/W 0 ft/min linear airflow Unit Test Conditions V mA STS-1 (see Note 1) mW STS-1 (see Note 1) mA STS-3 (see Note 1) mW STS-3 (see Note 1) mA STM-1 (see Note 1) mW STM-1 (see Note 1) TXC-04251-MB Ed. 4, March 2000 ...
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... INPUT PARAMETERS FOR TTLp, INPUT PADS WITH INTERNAL 25 µA PULL UP * Parameter Min V 2 Input leakage current Input capacitance * Note: TTLp inputs can be disabled for device testing by applying a low to the TEST pin (pin 145). TXC-04251-MB Ed. 4, March 2000 DATA SHEET Typ Max Unit V 1.65 V µ ...
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... DATA SHEET Typ Max Unit 4.0 mA -4.0 mA µA ±10.0 Typ Max Unit 4.75 ≤ 4.75 ≤ V 0.8 V µA ±1 8 QT1M TXC-04251 Test Conditions = 4.75 -4 4.75 4 Test Conditions ≤ 5.25 DD ≤ 4.75 -8 4.75 8 TXC-04251-MB Ed. 4, March 2000 ...
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... TCLKI =1. For NRZ operation, TNIn may be used to input an external loss of signal indication. Otherwise, this pin must be held high. Parameter TCIn Clock period TCIn clock low time TCIn clock high time TPIn/TNIn data set-up time before TCIn↓ TPIn/TNIn data hold time after TCIn↓ TXC-04251-MB Ed. 4, March 2000 DATA SHEET + CYC t ...
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... RCOn clock low time RCOn clock high time RPOn/RNOn data delay from RCOn↑ DATA SHEET t CYC t t PWL PWH t OD Symbol Min Typ t 637 CYC t 318 PWL t 318 PWH t 0 QT1M TXC-04251 Max Unit 658 ns 329 ns 329 ns 5.0 ns TXC-04251-MB Ed. 4, March 2000 ...
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... A(7-0), APAR data out (from tristate) delay from DCLK↑ A(7-0), APAR data to tristate delay from DCLK↑ ADD add indicator delayed from DCLK↑ AIND add bus indication output delay from DCLK↑ TXC-04251-MB Ed. 4, March 2000 DATA SHEET t CYC ...
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... SU(1) t 5.0 H( SU(2) t 5.0 H( SU(3) t 5.0 H(3) t 6.0 D(1) t 6.0 OD(2) t 6.0 OD(3) t 6.0 OD(1) t 6.0 OD( QT1M TXC-04251 Data STS-1 #3 STS-1 #1 OCCURS EVERY FOUR FRAMES WHEN PROVIDED IN PLACE OF THE H4 BYTE J1 STS STS STS STS-1 #3 Typ Max Unit 51. TXC-04251-MB Ed. 4, March 2000 ...
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... A(7-0), APAR data out (from tristate) delay from ACLK↑ A(7-0), APAR data to tristate delay from ACLK↑ ADD add indicator delayed from ACLK ↑ AIND add bus indication output delay from ACLK↑ TXC-04251-MB Ed. 4, March 2000 DATA SHEET t CYC ...
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... ADD BUS VT/TU TIME SLOT OD(4) SELECTED WHEN ENABLED Symbol Min t CYC SU(1) t 5.0 H( SU(2) t 5.0 H(2) t 6.0 OD(2) t 6.0 OD(3) t 6.0 OD(1) t 6.0 OD( QT1M TXC-04251 OCCURS EVERY FOUR FRAMES WHEN ENABLED V1 STS STS STS-1 #3 Typ Max Unit 51. TXC-04251-MB Ed. 4, March 2000 ...
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... UPAD(7-0) data available delay after RD↓ UPAD(7-0) data delay to tristate after RD↑ ALE wait time after RD↑ SEL set-up before RD↓ SEL hold time after RD↑ RD wait after ALE↓ RD pulse width TXC-04251-MB Ed. 4, March 2000 DATA SHEET t t H(1) H(2) ...
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... WR wait after ALE↓ WR pulse width DATA SHEET t W( SU(2) H(1) Address Data t SU( W(2) PW(2) Symbol Min Typ t 20 PW(1) t 0.0 W(1) t 5.0 SU(1) t 3.0 H(1) t 3.0 SU( H(2) t 0.0 SU(3) t 0 PW( QT1M TXC-04251 t H(2) t H(3) Max Unit TXC-04251-MB Ed. 4, March 2000 ...
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... TCK clock low time TMS setup time before TCK↑ TMS hold time after TCK↑ TDI setup time before TCK↑ TDI hold time after TCK↑ TDO delay from TCK↓ TXC-04251-MB Ed. 4, March 2000 DATA SHEET Figure 12. Boundary Scan Timing PWH t ...
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... In the dual unidirectional ring mode of operation, a VT/TU is dropped from the A (or B) Drop bus, with the return path both the A and B Add buses. Timing for the VT/ added to the A (or B) Add bus is derived from either the A (or B) Drop bus, or from the A (or B) Add bus. DATA SHEET - 29 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... The control bit settings for format selection are given in the table shown below. When the STS-1 format is selected, the buses are configured to operate at a bus rate of 6.48 Mbyte/s, instead of 19.44 Mbyte/s for VC-4/AU-3/STS-3 formats. STS-1 Format STS-3 Format STM-1 AU-3 Format STM-1 TUG-3/VC-4 Format TXC-04251-MB Ed. 4, March 2000 DATA SHEET TnSEL1 TnSEL0 RnSEL 0 ...
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... AU-3/TUG-3 B, STS-1 #2 AU-3/TUG-3 C, STS-1 #3 VT/TU Group Number 1 VT/TU Group Number 2 VT/TU Group Number 3 VT/TU Group Number 4 VT/TU Group Number 5 VT/TU Group Number 6 VT/TU Group Number 7 0 VT/TU Number 1 1 VT/TU Number 2 0 VT/TU Number 3 1 VT/TU Number 4 TXC-04251-MB Ed. 4, March 2000 ...
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... Note: For UCHnE=1 and USCHnE=1, substitute all occurrences of “Unequipped” in the table with “Unequipped Supervi- sory”. ** Note: Only multiplexed mode is effected by the UEAME control bit. All other modes operate independently of the state of the UEAME bit. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Add/Drop Mode ...
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... J1, V1, and other signals are shown in the Timing Characteristics section. DATA SHEET DRPBT* X Add bus timing selected. X Drop bus timing selected. 0 Add bus timing selected. ABUST pin disabled. 1 Drop bus timing selected. ABUST pin disabled. Bus Timing Selection - 33 - QT1M TXC-04251 Action TXC-04251-MB Ed. 4, March 2000 ...
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... The H4 byte is monitored for multiframe alignment when enabled. Loss of multiframe alignment is declared (AnDH4E, BnDH4E) if two or more H4 byte values differ from those of a 2-bit counter for two consecutive mul- tiframes. Recovery occurs when four consecutive sequential H4 byte values are detected once. TXC-04251-MB Ed. 4, March 2000 DATA SHEET ...
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... Drop bus V1 pulse in the A/BDC1J1V1 signal determines dropped VT/TU V1 byte starting location, A/B Drop bus H4 multiframe detector disabled. V1 pulse in add bus A/BAC1J1V1 signal is ignored. Add bus V1 alignment determined by the V1 pulse in the add bus A/BAC1J1V1 signal. Add Bus V1 Reference Selection - 35 - QT1M TXC-04251 Action TXC-04251-MB Ed. 4, March 2000 ...
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... If an alarm has recovered (i.e the off state) prior to the read cycle, and during the read cycle of the regis- ter that contains the alarm, the alarm occurs again, it will not result in a latched alarm indication. TXC-04251-MB Ed. 4, March 2000 DATA SHEET ...
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... Port n Alarms (PORTn) AnNDF AnRDI AnRFI BnNDF BnRDI BnRFI TAnFE TBnFE TnLOS - 37 - QT1M TXC-04251 PORT2 PORT1 P2MSK P1MSK RPT1A RPT1B TFIFO1A TFIFO1B RFIFO2 RFIFO1 A2UAISI A1UAISI A2DH4E A1DH4E B2UAISI B1UAISI B2DH4E B1DH4E AnUNEQ AnSLER BnUNEQ BnSLER TnLOC TnDAIS TXC-04251-MB Ed. 4, March 2000 ...
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... Note Don’t Care TXC-04251-MB Ed. 4, March 2000 DATA SHEET Interrupt LATEN Mask Bit alarm event indication, or interrupt register indication Alarm event register sets on positive levels of an alarm; no software or hardware interrupt indications Alarm event register sets, and software interrupt indication occurs, on positive levels of the alarm ...
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... Negative Justification: Inverted 5 D-bits and accept majority rule Positive Justification: Inverted 5 I-bits and accept majority rule SS-bits (VT Size for 1544 kbit/s, DATA SHEET Pointer Bytes Bit Assignment - 39 - QT1M TXC-04251 V2 Byte TXC-04251-MB Ed. 4, March 2000 ...
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... The pointer value is a binary number with a range 103 for the 1544 kbit/s format. The pointer offset indi- cates the offset from the V2 byte to the first byte in the VT1.5 mapping. The pointer bytes are not counted in the offset calculation. The pointer offset arrangement for this format is shown below. TXC-04251-MB Ed. 4, March 2000 DATA SHEET 1544 kbit/s TU-11/VT1 ...
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... New Offset) (Accept New Offset AIS_ind (Offset Undefined) LOP 8 x inv_point (Offset Undefined) NDF_enable (Accept New Offset AIS_ind (Offset Undefined QT1M TXC-04251 3 x AIS_ind DEC (Offset Undefined) dec_ind (Decr. Offset any_point 3 x new_point 3 x AIS_ind AIS TXC-04251-MB Ed. 4, March 2000 ...
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... Recalculate the value of 'C' by subtracting the oldest sample and adding the newest, and calculate a new leak rate, as described in Note 5 (e.g., using S2 through S11). 8. Continue to repeat the steps described in Notes 5, 6 and 7 until AIS, LOP , LOS or NDF is received or until you reset the QT1M. TXC-04251-MB Ed. 4, March 2000 DATA SHEET 10 SEC ...
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... Unequipped Signal Label 1 Remote defect (old equipment). RDI Bit Assignment AnRDIS BnRDIS Action 1 Remote Server Defect Indication, and old equip- ment RDI indication (Bit 8 in the V5 byte). 0 Remote Payload Defect Indication. 0 Remote Connectivity Indication. RDI Alarm Definition - 43 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... The three control bits TnRDIS, TnRDIP and TnRDIC may only be activated one at a time, since activation of two or more at the same time can cause decode errors. TXC-04251-MB Ed. 4, March 2000 DATA SHEET ...
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... Second Justification Control Byte Bit 3 Register 7 DATA SHEET Other Bytes J2 Byte Bytes - Information V3 Byte Z6 Byte Other Bytes O-bit Placement in a 1544 kbit/s VT/TU First Justification Control Byte O-bit Assignment Memory Map - 45 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... The table below shows the bit assignment for the first two bytes. Bit 1 Row 1 1 Row 2 1 The third byte (and the other 6 bytes in the column) are assigned as fixed stuff. Bytes which are designated as stuff (cross-hatched) will be in the high impedance state. TXC-04251-MB Ed. 4, March 2000 DATA SHEET TUG-3A TUG- ...
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... NRZ Rail AMI/B8ZS Coder Bypass Line Loopback Data &Clock Rail AMI/B8ZS Decoder Bypass Line Loopback NRZ - 47 - QT1M TXC-04251 Facility Loopback Receive Data & Clock (NRZ, Rail) T1 Line Facility Loopback Data &Clock Transmit Data & Clock (NRZ, Rail) TXC-04251-MB Ed. 4, March 2000 ...
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... B8ZS encoding, which gives the maximum delay. On the Transmit side (T1 to SONET/SDH) the maximum delay is approximately 85 clocks with a nominal delay of around bit times. The delay is less for AMI or NRZ than for B8ZS decoding. TXC-04251-MB Ed. 4, March 2000 DATA SHEET ...
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... During the Capture_IR state of the TAP controller state machine, 001 is loaded into the 3-bit instruction regis- ter. 1. The BSDL file for this device contains further information regarding the operation of the TAP . This file is available upon request from the Applications Engineering department of TranSwitch. DATA SHEET - 49 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... Specific control of the TRS lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. This lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the Test Access Port (TAP) controller during power-up of the QT1M. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Figure 16 ...
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... Unused: Observe-only Cell 158 Reserved Unused: Observe-only Cell 157 ABUST A/B Add Bus Timing Select 156 Reserved Unused: Observe-only Cell 155 RESET Low-Active Device Reset 153 Reserved Unused: Observe-only Cell 152 INT/INT Interrupt Out-Polarity Selectable - 51 - QT1M TXC-04251 Comments TXC-04251-MB Ed. 4, March 2000 ...
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... Input 69 Control 70 3-State Input 74 Input 75 Input 76 Input TXC-04251-MB Ed. 4, March 2000 DATA SHEET Pin # Pin Name -- hwint_enb Output Enable for 152 150 INTSH Interrupt Sense High 149 ALE CPU Interface Add. Lat. En. 148 WR CPU Interface Write Line 147 RD CPU Interface Read Line ...
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... BAPAR B Add Parity Bit 76 BA7 B Add Bus Data -- Ba6p_enb Output Enable for 75, 76 BA6 B Add Bus Data 73 BA5 B Add Bus Data 72 BA4 B Add Bus Data -- Ba35_enb Output Enable for 71, 72 BA3 B Add Bus Data - 53 - QT1M TXC-04251 Comments TXC-04251-MB Ed. 4, March 2000 ...
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... Bidirectional Pins have two BSR cells, one Observe-Only BS Cell for the Input and an Observe & Control BS Cell for the Output. In addition there will be a Control & Observe Cell for the direction control pin, although in most cases these serve two or more pins. TXC-04251-MB Ed. 4, March 2000 DATA SHEET ...
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... STS-1 VT1.5 (1.544 Mbit/s) Multiplex Format The following diagram and table illustrate the mapping of the 28 VT1.5s into a STS-1 SPE. Column 1 is assigned to carry the path overhead bytes. VT1.5 3 COLUMNS 1.5 1.5 1.5 1 STS-1 SPE DATA SHEET 1.5 1.5 1.5 1.5 1 QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... QT1M TXC-04251 4CH (Port 1), 7CH (Port 2), ACH (Port 3) and DCH (Port 4) Registers VT Note: Columns 30 and 59 carry fixed stuff bytes. Column 1 is assigned for the POH bytes. TXC-04251-MB Ed. 4, March 2000 DATA SHEET STS-1 Mapping VT1.5 Column Numbers Selected 34, 63 ...
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... The following diagram and table illustrate the mapping of the VT1.5/TU-11s into a STS-3/AU-3 SPE. Each STS-3 carries three STS-1s. Column 1 in each STS-1/AU-3 is assigned to carry the path overhead bytes. VT1.5 3 COLUMNS 1.5 1.5 1.5 1.5 1 STS DATA SHEET 1.5 1.5 1.5 1.5 1.5 1 STS-3/AU-3 SPE - 57 - QT1M TXC-04251 1.5 1.5 1.5 1 261 TXC-04251-MB Ed. 4, March 2000 ...
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... STS-1 #1, AU Note: Columns 88, 89, 90, 175, 176, 177 are fixed stuff. TXC-04251-MB Ed. 4, March 2000 DATA SHEET STS-3 AU-3 Mapping 4CH (Port 1), 7CH (Port 2), VT/TU VT ACH (Port 3), TU Column DCH (Port 4) # Numbers Registers ...
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... TU-11 - VC-4 Multiplex Format Mapping The following diagram and table illustrate the mapping of TU-11s into a VC-4. The QT1M provides control bits for enabling the Null Pointer Indicators (NPIs) for the columns indicated. 3 COLUMNS TUG TUG VC DATA SHEET TU- QT1M TXC-04251 261 TXC-04251-MB Ed. 4, March 2000 ...
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... TUG-3 A TXC-04251-MB Ed. 4, March 2000 DATA SHEET TU-11 - VC-4 Multiplex Format Mapping 4CH (Port 1), 7CH (Port 2), ...
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... Reserved 05H-0FH Common 10H-21H Registers A Bus 22H-25H B Bus 26H-29H Port 1 30H-5FH Port 2 60H-8FH Port 3 90H-BFH Port 4 C0H-EFH Reserved F0H-FFH Bit 6 Bit 5 Bit Revision (Version) Level Mask Level (0000 QT1M TXC-04251 Bit 3 Bit 2 Bit 1 Bit Growth (0000) TXC-04251-MB Ed. 4, March 2000 ...
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... R( R(L) BDLOC 27 R BDLOC 28 R( Note: Status codes are R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Bit 6 Bit 5 Bit 4 MOD0 AAHZE BAHZE BLOCK DRPBT ABD LATEN TAISE APE IPOS INEG DISRFI DV1SEL ...
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... Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 RnEN TnB8ZS Unused Bit 2 Bit 1 Bit 0 AnRFI AnUNEQ AnSLER AnRFI AnUNEQ AnSLER AnNJ Counter An Rx Label Unused Unused Bit 2 Bit 1 Bit 0 BnRFI BnUNEQ BnSLER BnRFI BnUNEQ BnSLER BnNJ Counter Bn Rx Label TXC-04251-MB Ed. 4, March 2000 ...
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... RnSETS RnSETC R/W * Note: Status codes are R=Read Only; R(L)=Read Only (Latched); R/W=Read/Write; W=Write Only. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Bit 6 Bit 5 Bit 4 Bit 3 BnRDIC BnRDIC Bn Receive J2 Byte Bn Receive Z6 Byte Bn Receive Z7 Byte Bn Receive O-Bits Bit 6 Bit 5 Bit 4 ...
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... Add bus timing selected. Add bus data derived from add bus timing signals. Hard- ware control of bus timing disabled Drop bus timing selected. Add bus data derived from like-named drop bus. Hard- ware control of bus timing disabled QT1M TXC-04251 Action TXC-04251-MB Ed. 4, March 2000 ...
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... RCLKI Receive T1 Line Clock Inversion: A common control for the four ports enables the T1 receive data signal to be clocked out on positive clock edges causes T1 data to be clocked out on negative clock edges. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description - Loss of pointer detected (A1LOP) ...
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... Odd parity check over drop data, SPE, and C1J1V1 for both A and B buses. 1 Odd parity check over drop data only. 0 Even parity check over drop data, SPE, and C1J1V1 for both A and B buses. 1 Even parity check over drop data only QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... Unused: This bit must be written DDIND Delay Drop Bus Indication Signal increases the delay of the drop bus indication signals (ADIND and BDIND) by one additional clock cycle. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description for: - A/B Drop H4 Error (A1DH4E, B1DH4E), when DV1SEL is 0 ...
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... DATA SHEET Description Description Add Action A B Unequipped or unequipped supervisory channel can be transmitted for the VT/TU selected on the A bus Unequipped or unequipped supervisory channel can be transmitted for the VT/TU selected on the B bus QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... Port 2 Interrupt Indication: Enabled when written into the P2MSK bit indicates that an alarm has occurred in one of the port 2 alarm registers. 0 PORT1 Port 1 Interrupt Indication: Enabled when written into the P1MSK bit indicates that an alarm has occurred in one of the port 1 alarm registers. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description Description - 70 - ...
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... FIFO (mask bits for bit 7 in registers 44, 74, A4, and D4) when PnMSK is set for port disables a receive FIFO error alarm for port n from causing an interrupt. DATA SHEET Description - 71 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... Port 1 Interrupt Mask Bit enables the Port 1 Interrupt Indication (PORT1). It permits a hardware interrupt and a software interrupt indication (INT) when an alarm has occurred in one of the alarm registers for port 1, when the corresponding RPT1A, RPT1B, TFIFO1A, TFIFO1B, RFIFO1 TPORT1 mask bit is set. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description - 72 - ...
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... The multiframe detector will continue to operate in a free running mode, but will lock to a new H4 sequence after one multiframe sequence has been received correctly. This H4 detector is disabled when the format is an AU-4 VC STS-1. This bit is forced power-up. DATA SHEET Description - 73 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... STS-1: When control bit SE1AIS indicates that AIS has been detected in the H1/H2 bytes for AU-3 A/STS-1 No the AU-4 VC-4 signal. When control bit SE1AIS indicates that AIS has been detected in the E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1 signal. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description ...
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... Leak average leak rate. A count of 1 one represents 8 frames multiframes Port 3 Rate the rate of occurrence of pointer movements from the number of counts read D9 Port 4 Value from the positive and negative stuff counters. DATA SHEET Description Description - 75 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... BYPASn Bypass CODEC of Port disables the AMI/B8ZS CODEC (coder and decoder) of port n for NRZ operation. This bit also works in conjunction with the TnB8ZS control bit, according to the following table: BYPASn Note don't care (0 or 1). TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description RnSEL ...
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... AIS, or should write RnEN, which will tristate the port n data and clock output pins. In this case, the TnSEL(1-0) bits should be set disable any data being added to the bus from the unassigned port. DATA SHEET Description - 77 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... The following alarms will not cause an unequipped indication alarm (AnDH4E) when DV1SEL Loss of pointer alarm (AnLOP) - VT/TU AIS alarm (AnAIS) - Upstream AIS detected (AnAISI) when HEAISE is 1 TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description (n is the STS-1 or AU-3 identifier ...
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... Port 1 7-0 Latched Same alarms as the corresponding address 4F, 7F, AF, DF bit positions, except that these alarms are latched. 7E Port 2 An Alarms AE Port 3 DE Port 4 DATA SHEET Description (n is the STS-1 or AU-3 identifier QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... B Drop Bus Port n New Data Flag Indication indicates that a New Data Flag (1001 or 0001/1101/1011/1000) has been detected in the V1 pointer byte for the VT/TU selected (i.e., bits 1-4 in the V1 byte are the inverse of the normal 0110 pattern or differ in only one bit). TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description ...
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... These two errors cause a single count if the CD Port 4 BLOCK control bit is set to 1. The counter saturates at full count and is cleared when it is read. DATA SHEET Description (n is the STS-1 or AU-3 identifier the STS-1 or AU-3 identifier QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
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... The two nib- bles written into this register location will be from the same frame. 44 Port 7-0 Latched Same alarms as the following address locations, except these alarm states are 174 Port 2 Tx latched. A4 Port 3 Alarms D4 Port 4 TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description - 82 - ...
Page 83
... AMI/B8ZS line codes. During a read cycle internal logic holds any new A7 Port 3 Counter count until the read cycle is complete, and then the counter is updated. This D7 Port 4 High counter is cleared on reset pulse, reset counter control bit = 1, or when it is Order read. Byte DATA SHEET Description - 83 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
Page 84
... The control bits for port n are not reset. This bit is self-clearing, and will reset B2 Port after the reset cycle is completed. E2 Port 4 6 RnSETC Reset Port n Performance Counters resets the performance counters to 0 for port n. This bit is self-clearing, and will reset to 0 after the reset cycle is completed. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Description - 84 - ...
Page 85
... TOBWZ is 0. Bits 7 through 4 correspond to bits 3 through 6 89 Port 2 O-bits in the second justification control byte. Bits 3 through 0 correspond to bits 3 B9 Port 3 through 6 in the first justification control byte. E9 Port 4 DATA SHEET Description - 85 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
Page 86
... INDEX PIN #1 SEE DETAIL “A” DEGREES Figure 17. QT1M TXC-04251 160-Pin Plastic Quad Flat Package TXC-04251-MB Ed. 4, March 2000 DATA SHEET 81 80 TRANSWITCH TXC-04251AIPQ 41 40 25.35 (SQ) 28.00 (SQ) 31.20 (SQ) 0.16 DETAIL “A” Notes: 1. All linear dimensions are in millimeters. 0.80 2. All dimensions are nominal unless otherwise indicated ...
Page 87
... ORDERING INFORMATION Part Number: TXC-04251AIPQ RELATED PRODUCTS TXC-02020, ART VLSI Device (Advanced STS-1/DS3 Receiver/Transmitter). ART performs the transmit and receive line interface functions required for transmission of STS-1 (51.840 Mbit/s) and DS3 (44.736 Mbit/s) signals across a coaxial interface. TXC-02021, ARTE VLSI Device (Advanced STS-1/DS3 Receiver/Transmitter). ARTE has the same functionality as ART, plus extended features ...
Page 88
... Global Engineering Documents 7730 Carondelet Avenue, Suite 407 Clayton, MO 63105-3329 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia Antipolis Cedex France TXC-04251-MB Ed. 4, March 2000 DATA SHEET Tel: 212-642-4900 Fax: 212-302-1286 Web: www.ansi.org Tel: 650-949-6700 Fax: 650-949-6705 Web: www ...
Page 89
... Fax: 215-697-1462 Web: www.dodssp.daps.mil Tel: 800-433-5177 (within U.S.A.) Tel: 503-693-6232 (outside U.S.A.) Fax: 503-693-8344 Web: www.pcisig.com Tel: 800-521-CORE (within U.S.A.) Tel: 908-699-5800 (outside U.S.A.) Fax: 908-336-2559 Web: www.telcordia.com Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or. QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
Page 90
... Updated Related Products section. 88-89 Made extensive changes to Standards Documentation Sources section. 90 Replaced List of Data Sheet Changes section to show changes from Ed Ed Updated Documentation Update Registration Form. TXC-04251-MB Ed. 4, March 2000 DATA SHEET Edition 4, March 2000 Edition 3, December 1997 Summary of the Change , t and ‘ ...
Page 91
... TranSwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. DATA SHEET - NOTES - - 91 - QT1M TXC-04251 TXC-04251-MB Ed. 4, March 2000 ...
Page 92
... TranSwitch Corporation 3 Enterprise Drive • • Shelton, CT 06484 USA Tel: 203-929-8810 - 92 - • • Fax: 203-926-9453 www.transwitch.com ...
Page 93
... Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453 e-mail (info@txc.com telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www ...
Page 94
... Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available. • TranSwitch Corporation 3 Enterprise Drive TranSwitch Corporation Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A. • ...